Design Of Some Key Cells Of High Speed High Resolution Pipelined ADC

In recent years, rapid progress in fields such as digital telephone transmission, satellite communications, radar, display, medical imaging, digital TV and high-speed internet access have provided a great demand on analog to digital convertor (ADC),meanwhile created more stringent requirement on their performance . Among varieties of ADC, pipelined ADC is the one which can achieve very high resolution as well as rather high speed.This paper study the design techniques of high speed high resolution pipelined ADC, focusing on the design of some key cells. At first kinds of non-ideal factors, error sources in the pipelined ADC are analyzed, and some key issues affecting its speed and resolution are discussed. These issues include the choice of per-stage resolution, digital error correction, and the speed of SC feedback amplifier. On the basis of these analysis, the key cells comparators, MDAC ,band-gap reference and the differential reference generator are designed for a 12bit 120MSPS pipelined ADC in a BiCMOS 0.35um technology. In the design, bottom-plate sampling is used in comparator and MDAD to reduce the charge injection and interference between pipelined stages; a clock voltage boosting technique is employed to improve the performance of the switch; and the comparator of the first stage adopt the capacitive coupling topology structure and preamplifier-latch comparator with positive feedback preamplifier to enhance the speed and resolution; a kind of amplifiers driven by a wide-band preamplifier is designed to speed up the setting of MDAC. The comparators and MDACs of other stages down the pipeline are scaled down to reduce power consumption and area. By high-order temperature compensation, the BGR achieve a lower temperature coefficient.All the blocks above are simulated with Cadence Spectre and the results show that they meet the requirement of 12 bit/120MSPS ADC system.