Design And Optimization Of Low Power High Speed Pipelined A/D Converter Dedicated For CMOS Image Sensor

Power dissipation is becoming an increasingly important issue in design of analog to digital converters as signal processing systems move into the high speed video systems, such as CMOS image sensor.Based on the chip processing ADC requiring both high speed and low power in CMOS image sensor, Pipeline architecture is considered as the best choice throngh analyzing the power consumption of several prototype ADCs. Sources of error in pipelined ADC and accuracy requirements of pipeline stage have been discussed in this thesis. And optimization techniques have been presented, which cover the key blocks of pipeline ADC, such as MDACs, Sub-ADCs, clock generator, digital correction circuits etc.This research focuses on minimizing power dissipation in high speed piplined ADCs. Lots of circuit techniques have been used to reduce power dissipation in this prototype, such as 1.5 bits per stage architecture, low power high performance enhance telescopic opamps in MDACs, scaling of pipeline stage, high speed low power dynamic comparators and a novel technique to minimize kickback noise in Sub-ADCs, modified non-overlapping clock etc. As a demonstration, design and implementation of 10bits 50MS/s pipelined ADC dedicated for CMOS image sensor is presented.In order to analyze and compare system performace, a 10bit 50MS/s pipelined ADC model has been set up in Matlab Simulink. The code density analyses show that the maximum DNL and INL are 0.2LSB and 0.4LSB respectively. The SNR, SINDR, SFDR and ENOB are 61.9dB, 61.5dB, 75.7dB and 9.93 respectively through FFT analysis. And the total power consumption is 47.8mW when operating at 50MSPS, which achieves the target of high speed low power pipelined ADC.The specific research contributions of this work include: (1) the trade-off between the per stage resolution and power dissipation (2) development of high performance low power MDAC design techique (3) research on high speed low power dynamic comparator and a novel low kickback noise technique (4) modified non-overlapping clock (5) modeling in Matlab Simulink, code desity and FFT analysis for system static and dynamic performance.