| Mobile communication experienced from analog radio to digital radio, from digital radio to software radio. Mobile wireless network has entered the era of 3G and 4G is going to be widely used in the near future. Electronic system of the broadband communication network, digital television network and the next generation Internet demand wider bandwidth and higher accuracy ADCs. For example, in radio transceiver systems, the ADC is preferred to be closer to the antenna in order to realize full-digital processing. Therefore, the ADC is one of the main challenges in building a wireless network. Pipeline ADC has been proven to be the most efficient in high speed high resolution ADCs with good tradeoff in speed, area, power and resolution. However, pipeline ADCs require high-gain and high-bandwidth op-amps to achieve good performance. Furthermore, aggressive device scaling in modern CMOS technology, coupled with low supply voltage operation, has made the design of op-amps difficult. To extend life-time of chip and ensure the application sustain long battery duration which powered by battery or wireless energy, designing low power ADC is becoming more critical. SAR ADCs(Successive approximation register analog-to-digital converter) have found their way into systems that would normally be considered as being entirely digitised as these digital systems are pushed to higher levels of performance. However, SAR ADCs rely on good component matching and the process, high precision high speed SAR ADCs are seldom reported in literatures both at home and abroad.Operational principle of SAR ADC is introduced in this thesis. Switching linearity of capacitive DAC referring to the capacitor mismatch is analyzed in detail. An approach to custom design the capacitive DAC is proposed. On the basis of the MDAC in pipeline ADC, a novel ADC named Pipeline-SAR ADC due to the fact that it is in essence consisted of SAR ADC and Pipeline ADC is proposed. The non-ideal effects in Pipeline-SAR ADC are discussed with corresponding solutions. System level analysis of the Pipeline-SAR ADC is proposed. In addition, several novel circuit blocks are proposed to achieve high speed, medium resolution and low power. Through the analysis of the Pipeline-SAR ADC, it is easy to draw the conclusion that by merging SAR ADC and Pipeline ADC, the two categories of ADC are such effectively combinedthat the prototype simply implies a new design method to achieve high speed, high resolution ADC with low power budget.The prototype was fabricated in SMIC 0.18μm CMOS technology. The post-layout simulation results show that the ADC achieves 84.6d B SFDR and 72.42 d B SNDR with Nyquist input at 50MS/s. The performance gets enormous better when low frequency input is applied. Even when input signal frequency is far beyond Nyquist rate, the ADC still achieves SFDR greater than 75 d B. The experiments found that measurement results fit in with post-simulation results. The chip draws 10.8m W from a single 1.8V supply. When 9.911111 MHz input signal is applied to the chip, it achieves 81.97 d B SFDR, 67.53 db SNDR. It turns to 77.13 d B SFDR and 67.01 d B SNDR when the frequency of input signal is increased to 24.111111 MHz. The DNL is within +0.536LSB/-0.676 LSB and the INL is within +0.959LSB/-1.025 LSB. |
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