Design Of Core Modules In A12-bit Pipeline ADC

With the development of CMOS technology, the system on chip (SoC) isintegrating more and more functional modules. High performance ADCs as animportant interface of the analog and digital system are widely used in mobilecommunications, high-definition video, digital signal processing, et al. The pipelineADC achieves a good compromise between speed, power, resolution, and chip area.The pipeline ADC is an ideal choice for system integration and portable electronicdevices for its flexible structure and the resolution of each stage. Therefore, the designand implementation of a12-bit20MS/s pipeline ADC is presented in this paper.This article describes the basic principle of the ADC, the key performanceparameters and several common ADCs. The pipeline ADC structure and workingprinciple are also introduced in this paper, after the analysis of non-ideality factors.This structure is composed of9stages with a3.5-bit in the first stage,1.5-bit/stagefrom the second to ninth stage and a3-bit Flash ADC in the last stage. Sample andhold circuit,3.5-bit MDAC,1.5-bit MDAC,4-bit Flash ADC, delay alignmentcircuits and digital correction circuits are designed in this paper. High-gain amplifierand bootstrap switches are used to guarantee the accuracy of the sample and holdcircuit. In order to guarantee the linearity and accuracy of the MDAC, a new MDACstructure and bootstrap switch with drive capability is used in the signal pathwaybetween the MDAC and SHA. According to scaling down technology,8stages ofMDACs with1.5-bit/stage are designed. In order to lower the consumption of ADC,we use the structure of fully differential switch-capacitor comparator. By using theFull-Custom method, delay alignment circuit and digital correction circuit aredesigned since the analog circuits are susceptible to the interference from digital parts.In the paper, the design of a12-bit20MS/s pipelined ADC is presented in detailsafter theoretical analysis and circuit optimization, based on the GF0.18um standardCMOS process using Cadence Spectre simulator. The measurement result shows that,its SFDR is69.72dB, INL is+0.87/-0.077LSB, DNL is+0.55/-0.67LSB, and ENOBis11.01bits.