System Analysis Of10Bits65MSPS Time-interleaved Pipeline ADC And MDAC Design

With development of digital signal processing technology and computertechnology，and the widely used of SDR idea, the requirements of the ADC is alsoincreasing.In the past few decades, data conversion device has also been extensively studied,time interleaved pipelined ADC can do a better tradeoff in accuracy,speed and power,so thatthe interleaved pipelined topology become the preferred solution of the high-speedhigh-precision and low-power ADC design.This paper based on0.13μm CMOS process,have designed a10bits65MSPSpipelined ADC for baseband sampling, power supply voltage is2.5V.1.5bit MDACperform both sample and hold function without the front-end S/H. This paper has done adetail system analysis of the pipelined ADC, introduced the evolution of MDAC dctransmission curve, described the nature of the whole evolution by analysis of ADCtransfer function. In the circuit design, this discussion focuses on the design of MDAC,modeling the MDAC behavior in the hold-phase by second-order system response, theMDAC’s signal set-up process is composed of two parts: small-signal and large-signalbuilding,by which we can get the performance requirements. The internal op amp usinghybrid cascode compensation two stage op-amp configuration, and the circuit design andsimulation, the measured gain and phase margin of the op amp is81.26dB and67.2°,unity-gain bandwidth of430MHz in tt process corner.Then have done the simulation ofop-amp and MDAC in ss and ff process corner, and compare their differences.By thecompare I get the conclusion that small signal build-up time is shorter than that we think.