Integrated Low-frequency Oscillator And 12b 10msps Pipeline, Adc Design

With the highly development of the digital technology, there is a growing trend for ADC in every field which can be summarized as high performance, low power consumption, small area. All of these urge the research of low power consumption and small area of integrate circuit become an emergency. This thesis improve a kind of low frequency oscillator, compared with traditional low frequency oscillator, which realize low power consumption, small area and stable frequency. Instead of operational amplifier which will consume a large current, this project adopt trigger, however, at the same time, this project also solve temperature swift problem. In other word, it can stabilize the frequency and also decrease the layout area. This low frequency oscillator has applied to ADC and sensor. The test results of tape-out show this kind of oscillator can satisfy the system requirement.At the same time, this thesis research system structure of 3V 12-bit 10Msps Pipeline CMOS ADC, the Pipeline structure satisfy the requirement of high speed and low power consumption, the whole ADC is composed by 12 stages, 1.5 bit in each stage. The reason for 1.5 bit is that it can maximize the frequency band since each stage only require gain of 2; in addition, it decrease the offset requirement of comparator, which simplify the design of comparator and can decrease the power consumption. I discuss and simulate sample and hold circuit, comparator circuit and×2 circuit in detail.In the first section, I analyze the information on ADC of aboard, which include the structure of ADC, the application domain, and illustrate the meaning of this research.In the second section, I analyze the structure of low frequency of oscillator, and improve a traditional low frequency oscillator, and compare indexes of power consumption, the layout area etc. The test results show that the oscillator can satisfy the whole chip system requirement.In the third section, I primarily introduce core modules of Pipeline ADC: sampling and hold module, CMOS switch, MDAC (multiple digital analog converter).I analyze the origin of charge-injection and clock feedback, also provide with the exact methods to solve them. I analyze how to choose the size of CMOS switch and the influence of CMOS switch to circuit. I present how the MDAC module to realize the input and output transfer function.In the fourth section, I analyze and simulate the concrete circuit. Firstly I introduce op amp in detail, present the concrete index of op amp, compare miller-compensation op amp, telescopic op amp and folded cascade op amp from the perspective of power consumption, output range, gain and bandwidth.I analyze fully differential op amp, presenting the exact circuit of common mode feedback circuit. When design high gain, high bandwidth of op amp. I discuss increase gain of op amp on the condition of without losing bandwidth, which is gain-boost technology. I compare op amp in two situations: with and without gain-boost technology. In addition, I present the theory of dynamic comparator, also substantiate the factors influenced dynamic comparator, providing with simulation results of dynamic comparator. Finally, I introduce sub digital analog converter circuit and fulfill of non-overlapping circuit.In the fifth section, I present tool of layout, principle of layout and steps of layout. This layout design is based on the Jazz 0.35um process. I provide with some portion of layout, and I analyze what should be taken attention from sample of layout, which includes how to match, how to minimize the interruption of noise and how to decrease the errors caused by process.