12-bit High-speed Pipeline ADC Key Circuit Design

With the rapid development of digital technology,high-speed and high-precision analog-to-digital converter(ADC)has been widely used in various fields.Pipelined ADC is one of the architectures of high speed and high precision analog-to-digital converter.It has relatively good tradeoff in three aspects: speed,precision and power consumption,and has been widely used in modern wireless communication systems.Therefore,it is of great significance to study high-speed and high-precision Pipeline ADC design for the development of communication field.The core and key circuits of pipelined ADC are the sampling holding circuit(S/H circuit)at the front end,the MDAC circuit and the sub-ADC circuit.The performance parameters of these key circuits directly affect the overall performance of pipelined ADC.Therefore,this paper focuses on the above circuits to analyze the core circuits and key technologies by simulation verification.Based on SMIC 0.18 ?m 1.8V CMOS process,a sample-holding circuit(S/H circuit),a 3.5-bit MDAC circuit and a sub-ADC circuit were designed for 12 bit 250MS/s pipeline ADC.Simulation results show that,The circuit was simulated under the condition of the input signal frequency of 12.7MHz,Effective Number of Bits(ENOB)of the front-end S/H circuit was 12.5 bits,Signal-to-Noise and Distortion Ratio(SNAD)was 77.3d B,and Spurious Free Dynamic Range(SFDR)was 78 d B.Secondly,the dynamic comparator was designed and simulated,the obtained misalignment voltage was 1.95 m V.And from the spectrum of the simulated bootstrap switch,SFDR was 109.9d B.Then,a two-stage reference voltage source circuit was designed to provide residual voltage for the amplification phase of MDAC.The temperature coefficient was 3.991ppm/°C(temperature range from-40°C to 100°C).Finally,sampling holding circuit and the first stage pipeline ADC circuit were simulated in whole.The output signals of the first stage circuitwere weighted and the waveform wasobtained for Fast Fourier transform(FFT)analysis.11.48 bits ENOB,70.89 d B SNAD,and 71.9d B SFDR were obtained,the overall simulation results met the design requirements.