The Design Of Comparators Applied In A Pipelined Folding And Interpolating Analog Digital Converter

So as to meet the demand of developing high speed, high resolution and low poweranalog digital converters, the research of designing comparators which can satisfy theapplication needs of analog digital converters has becoming a hot spot. Based on thepreamplifier-latch theory, this work shows a CMOS comparator, which will be appliedin a high speed pipelined folding and interpolating analog digital converter. Thiscomparator consists of a preamplifier with distributed T/H circuits and a dynamic latch,with a bistable structure as its core, which is build up by two inverters end-to-endconnected. The preamplifier takes a parallel connected structure of positive and negativeresistors as its load, which makes it possible to achieve both big bandwidth and highgain, also effectively increases the response speed and decreases the input offset voltageof the comparator. In order to guide the real circuits design, the work establishes asystem level model for the comparator by the software platform ofMATLAB/SIMULINK. Based on the detailed circuits design, a qualitative andquantification analysis of the offset voltage of the comparator is given in this work. Theanalysis results are validated through the Monte Carlo simulation. With the use of theobtained results, a optimization of the offset voltage of the dynamic latch is given.Based on the SMIC0.18μm1P6M1.8V mixed-signal CMOS foundry, a designingvalidation is got through Cadence Spectre simulation software. Simulation results showthat the transition delay under worst cases is610ps, the input offset voltage is14.1848mV and the average power dissipation of the whole comparator under regularoperation is0.2829mW which meet the application demand of the high speed pipelinedfolding and interpolating analog digital converter.