The Key Circuits Design Of Folding Interpolation A/D Converter

Compared with fully parallel ADC, the folding interpolation ADC, which is based on the combination of folding technique and interpolation technique, reduces power consumption while maintains high speed. So the folding interpolation ADC is widely used in the fields of medical equipment, digital gauges, communication equipment, satellite receiving systems, radar equipment, consumer electronics and others, which is becoming a hot research topic in the field of high-speed ADCs.First, this paper introduces the research background, significance and current situation of high-speed ADCs. Then the working principle of ADC is introduced systematically and depending on the sampling frequency, ADCs are divided into two types to be introduced and taken for example. In the meanwhile, some important performance parameters of ADC are given. Next, the work principle and implementation of the folding and interpolation ADCs as well as the design idea of this paper are given, while selection of the coefficients of folding and interpolation is analyzed in detail. Last, the overall structure of the system is finalized. Considering that the folding technique can reduce the number of comparators and interpolation technique can reduce the number of pre-amplifiers, the structure formed by folding and interpolation can guarantee the high-speed characteristics of ADC with less power consumption and area. This paper finally adopts four parallel folds which has folding coefficient of 8 and interpolation circuit which has interpolation coefficient of 8 to complete the converting of the lower five bits, while using fully parallel architecture to convert the upper three bits. In addition, the whole circuit in this paper is fully differential, which can suppress the common mode noise, reduce the charge injection effect and increase the dynamic range of the input signal.In the part of key circuits design, the specific design of reference voltage circuit, pre-amplifier circuit, folding circuit, interpolation circuit, comparator circuit and digital coding circuit is given as well as some simulation results. Among them, in the section of pre-amplify circuit design, the structure has been improved based on the traditional one; high-speed, high-precision and low-power comparator circuit is designed, of which offset voltage is only 1.5mV; in the section of digital encoding circuit, error correction circuit is designed to improve the conversion precision.Based on the TSMC 0.18μm CMOS process, with the sampling frequency of 500MHz and power supply voltage of 1.8V, we use tool of Cadence’s Spectre to simulate the circuits when input signal is sine wave with frequency of 212.89MHz. The results show that the SNR is 45.88dB, SNDR is 44.19dB and ENOB is 7.33 bit, which meet the design requirement.