| Successive approximation register analog-to-digital converters(SAR ADCs) are widely used in medium-speed medium-high-resolution applications such as medical devices, precision instruments, industrial imaging and so on, due to its simple structure,small size,low power,easy integration,etc. The main and most intractable factor affecting the accuracy of the SAR ADC is the matching of capacitors, so the capacitor mismatch must be calibrated in order to achieve high-precision SAR ADC. The traditional calibration methods are implemented by analog circuits. However, the cost of this technique is so high, and it is vulnerable to mechanical stress during the package. With the development of CMOS process, the advantages of digital circuitry in terms of speed, density, and integration are much clearer. Digital calibration has become the mainstream of the current calibration techniques.Firstly, a 12-bit low-power SAR ADC is designed in this thesis. Based on MCS switching procedure, a novel energy-efficient capacitor switching procedure is proposed.One-side-fixed technique is proposed to gain one bit of resolution without increasing the number of capacitors by taking advantage of the dummy capacitor in the last conversion step. Furthermore, the operational principle of bootstrap switch is analyzed, especially the detailed analysis of offset and noise of dynamic comparator. Finally, a novel SAR logic control technology is proposed by inserting the SAR logic circuits into level-shift circuits to reduce the complexity of the DAC control logic, enable high-speed and low-power operation and reduce the chance of race and hazard of the combinational logic circuit at the same time. Based on the SMIC 0.18μm 1P6 M CMOS process, these techniques are applied to a 12-bit SAR ADC without calibration. Test results show that at 1.8V supply voltage, 2MS/s sampling frequency, near Nyquist input frequency, the proposed ADC achieves SNDR of 67.26 d B. The peak DNL and INL are +0.66/-0.64 LSB and +0.75/-0.74 LSB, respectively. The ADC only consumes 183.3μW, so it achieves a FOM value of 48.63 f J/conversion-step. The performance is nearly international standards.For more accurate application, an all-digital foreground calibration 16-bit 1MS/s SAR ADC is proposed based on the same process. A detailed analysis of the calibration based on Sub-Radix-2 principal is presented in the thesis. It mainly focused on how to choose the radix values and the determination of the number of conversions for a given capacitor mismatch in sub-radix-2 structure. Then it was applied to a 16-bit 1M/s SAR ADC using a perturbation-based calibration. Followed by the analysis of its overall structure and calibration network structure and principle, elaborated on the timing of the whole circuit in calibration mode. A new perturbation circuit is proposed, this structure does not require additional capacitors to inject the perturbation signal, it just changes the timing of the voltage switching of 5th capacitor?s bottom plate in the existing capacitor array. The proposed circuit can overcome overheading of the additional circuitry, increasing of the DAC total capacitance, increasing of the power consumption and other issues in traditional circuit. Subsequently, a high-speed high-precision comparator with offset cancellation technique is analyzed and designed. Finally, the design of digital calibration modules is analyzed in detail from the aspects of design method, interface signals and module function. According to the pre-simulation, the SAR ADC designed in this thesis can achieve the results as follows, at 1.8V supply voltage, 1MS/s sampling frequency, 250 k Hz input frequency, it achieves SNDR of 67.26 d B, ENOB of 12.24 before calibration and SNDR of 93.64 d B, ENOB of 15.26 after calibration. AMS simulation results also show that the analog part consumes approximately 1.2m W; The synthesized results by DC display that the digital calibration part consumes 1.98 m W, so the total power consumption of the ADC is 3.18 m W. |
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