A Study Of The Calibration For Matching Errors In High Speed, High Resolution CMOS D/A Converters

The current steer architecture is the ideal architecture for high speed, high resolution D/A converters. Since variations in the process cause the oxide thickness, threshold voltage and mobility to vary, the unit currents are unequal, which affects the performance of the D/A converter. There are two ways to overcome the matching errors, one is to improve the intrinsic matching,the other is to calibrate the nominally identical currents. The calibration technology means to adjust the currents of the current source matrix, so the matching error could be canceled.This thesis mainly concerned with the calibration of the current steer D/A converter, focuses on the systematic design of the matching error calibration and a novel matching error calibration method designed with the systematic design concept. Through the analysis of existing current steer D/A converter calibration method, the thesis proposed the systematic design of the matching error calibration. With the systematic design concept, a calibration method would be proposed easier.In accordance with the systematic design concept, this thesis designed a novel matching error calibration method, The method summarized as follows: during the CP test, the current errors caused by device mismatching are measured, a computer specified the calibration currents needed to adjust the errors and the values of the calibration currents are saved in the build-in ROM; when the D/A converter begin to work, the information stored in the ROM control the build-in calibration sub-D/A converters to output the calibration currents, these currents combined with the original currents make the output currents of D/A converter accurated. Although the resolution of the method is limited by the resolution of the CP test, the calibration method could achieve the design goals; moreover, this calibration method could reduce the current steer D/A converter power-up time.