Design Of16Bit1MS/s CMOS SAR A/D Converter And Calibration

Successive approximation register analog-to-digital converters (SAR ADCs) arewidely used in medium-speed medium-high-resolution applications due to its simplestructure，low power，small size，easy integration，etc. To meet the demands of precisioninstruments, medical devices and industrial imaging，the high resolution SAR ADCdesign is becoming more critical. The main factors affecting the accuracy of the SARADC is the capacitance matching, so the capacitor mismatch must be calibrated in orderto achieve high-precision SAR ADC. The traditional calibration methods areimplemented by analog circuits. Since the scaling of CMOS device dimensions offersclear advantages for digital circuitry in terms of density, speed, and integration, itbecomes advantageous to push calibration into the digital domain if possible.First, a novel structure for high resolution SAR ADC is proposed in this thesis. Byanalyzing the effect of parasitic capacitor and capacitor mismatch, a behavioral modelin Matlab is proposed and simulation result confirms the theoretical analysis.Furthermore, detailed analysis of offset of high-resolution comparator is presented. A16-bit1MS/s SAR ADC is designed in TSMC0.18μm CMOS technology in Cadence.At3.0V supply voltage, the ADC achieves SNDR of96.8dB. At last, calibrationtechnology of SAR ADC is analyzed and detailed analysis of digital calibration usingthe “Split ADC” architecture is presented. A behavioral model of the digital calibrationusing the “Split ADC” architecture in Matlab is proposed and simulation resultsdemonstrate the reliability of the calibration technique.