Research On High Resolution SAR ADC And Calibration Techniques

Analog to Digital converter?ADC?converts analog information to digital information,which is widely utlized and of great importance.Successive Approxmation Register?SAR?ADC is simple in architecture,absence of the operational amplifiers,low in power and high in energy efficiency,friendly to the scaling CMOS technology.The SAR ADC is one of the alternative architectures to achieve high Figure of Merit?FoM?.So it has been a hotspot in recent years and has a broad prospect in various fields such as the Internet of thing,automotive electronics,industrial electronics,medical electronics and advanced instruments.In these applications,higher requirements are put forward for high resolution SAR ADC.However,there is a few literatures related to high resolution SAR ADC.Therefore,it is of great significance to study the high resolution SAR ADC.On the basis of existing research,the effects of the various non-ideal factors on the accuracy of SAR ADC are comprehensively analysed,a summary about the existing digital calibration techniques are given and two feasible high resolution SAR ADCs are proposed.The research contents of this paper include:Firstly,the influence of capacitance mismatch and parasitic capacitance in the different capacitor array of SAR ADC is analyzed.The relationship between the capacitor mismatch and the non-linearity of Capacitor DAC are deduced.The effect of the parasitic capacitance on the Capacitor DAC output voltage is explained.Considering the requirements of system area and precision,two kinds of structures are obtained for high resolution application:binary weighted with attenuation capacitor and C-R hybrid structure.In order to realize the high FoM ADC,the binary weighted with attenuation capacitor is studied,and the influence of the capacitor mismatch and the parasitic capacitance on the linearity is deduced under different segments.Aiming at the problem of fractional bridging capacitance?C_b?,an improved binary weighted with attenuation capacitor?kBWA?is proposed.The effect of capacitance mismatch and parasitic capacitance is analyzed and is verified through the behavioral simulation.The structure implements the integer C_b by introducing two additional design variables:the capacitance amplification factor k and the redundant capacitance C_dl.When k=1,the area and resolution of this structure is consistent with that of the traditional binary weighted with attenuation capacitor.With the increase of k,the capacitance mismatch decreases,which improves the precision of the system.The system designer has the flexibility to choose the values of k and C_b to achieve a better compromise between area,resolution and power consumption.Second,with the evolution of CMOS integrated circuit processes,lower supply voltage and transistor intrinsic gain make it difficult to design high-resolution analog circuits,requiring trimming,analog calibration,or digital calibration techniques to achieve high-resolution analog circuit.The digital calibration techniques can be implemented in a more diverse way,adaptable to the process,with high integration,so the use of digital calibration technique to design high-resolution ADC has become a hot and difficult spot.On the basis of summarizing the existing digital calibration technique of high-resolution SAR ADC,two new digital calibration schemes are proposed,which are offset double injection calibration based on integer sub-binary weighted with attenuation capacitor and the split-ADC digital calibration scheme based on dynamic element matching.The working principle and implementation algorithm of the two schemes are analyzed and deduced in detail,and verified by behavioral simulation.The results show that both schemes can effectively reduce the error of the capacitor array and improve the accuracy of the ADC.Thirdly,on the basis of the above analysis and summarization,aiming at the non-ideal factors of the traditional binary weighted with attenuation capacitor,this paper proposes an offset double injection calibration based on integer sub-binary weighted with attenuation capacitor to obtain a 16bit 1Msps SAR ADC.Because the traditional fractional sub-binary capacitor array can not be realized by using the unit capacitor.So the capacitor mismatch will be increased and this traditional structure is difficult to be utilized in the binary weighted with attenuation capacitor.Above all,the integer sub-binary capacitor array is employed.The relationship among the sub-binary radix r,the capacitance mismatch and the conversion times is discussed.The LMS algorithm is introduced in the offset double injection digital calibration scheme and reduces the error value of each bit weight to improve the accuracy of ADC.In addition,the key modules in the circuit are optimized,such as the bootstrap switch that eliminates the body effect,the multi-stage cascaded automatic-zero comparator,and the new offset signal injection circuit.This prototype is manufactured in the SMIC 0.18?m CMOS process and the layout design,the post-simulation,tape-out and test are completed.The results show that the FoMs of this prototype is 170.77dB,the effective number is 14.46 bits,the DNL is-0.625/0.688 LSB,and the INL is-0.813/0.938 LSB,and the high resolution SAR ADC is realized.Finally,in order to further improve the accuracy of ADC,this paper presents a split-ADC digital calibration scheme based on dynamic element matching,and designs a 16-bit1Msps SAR ADC.At first,the basic principle and different implementation methods of dynamic unit matching technology are introduced.In order to reduce the hardware cost of the control circuit,a binary coding dynamic element matching technique is proposed.Then,the split-ADC digital calibration scheme based on the dynamic unit matching technique is introduced,and the precision is improved by LMS algorithm.In order to further reduce the area and power consumption,a multi-segment capacitor array structure,with redundant bits are used to avoid missing-level error,to ensure that the digital domain can be calibrated.The key modules in the circuit are optimized,such as the low-power dual mode cascade comparator,dynamic element matching control logic.A high precision band-gap reference is also proposed.This prototype is manufactured in the SMIC 0.18?m CMOS process and the layout design,the post-simulation,tape-out and test are completed.The results show that the FoMs of this prototype is 170.47dB,the effective bit is 15.04 bits,DNL is-0.422/0.536LSB,and the INL is-0.721/0.758 LSB,and the high resolution SAR ADC is obtained.