Investigation On High Performance Pipeline A/D Converter For CMOS Image Sensor

In mixed signal systems, Analog-to-Digital Converter (ADC) which has wide applications in many fields is a crucial portion. Because of its configuration advantages of low power consumption, high speed and high accuracy, the pipelined ADC has been used in more and more extensive application fields. The research tries to achieve a high performance pipeline ADC for the CMOS image senor, and an experimental low power 10bit 50MHz pipeline A/D converter which is based on SMIC 0.18um CMOS process is implemented.The paper includes the content as followed:First, a system model of 1.5b/stage pipeline ADC built in Matlab-Simulink has been introduced. In order to analyze and compare system performance, ideal math model has been set. Then non-idealities such as thermal noise, comparator offset, and gain error of MDAC have been considered respectively in that model. Some data has also been gained in that simulation to steer the detailed circuit design.Second, this research mainly focuses on power consumption and linearity. It consists of some aspects. For example, traditional two non-overlapping 1.5bps with redundant correction has been used as to reduce comparator offset requirement. Flip-around SHA has been set in order to minimize noise and power dissipation in S/H stage. Capacitor scaling technology has been adopt to reduce back-end OTA requirement. Trading off between noise and power, sampling capacitor and OTA current have been optimized. In addition, boost-strapping switch is in loop in order to improve the linearity of ADC. A novel low kick-back noise technique results from time trimming.Third, as for the digital part, the system timing has been carefully arranged by designing the clock generator. And the rational system timing guarantees the reliability of the system. In addition, some other assistant circuits such as latch array, adders are designed to complete the function or be a part of digital correction module.Fourth, capacitor mismatch calibration which is used for high resolution pipeline ADC has been introduced,then small signal model is analysed and simulated. OTA and comparator share technology is recommended to lower power consumption further more.