| Phase-locked loop(PLL) is widely used for achieving high precision clock signal and wireless modem technology and data recovery in clock synchronization, and other functions. With the modern social becoming more informationize, the PLL requires higher performance. The compromise between the PLL circuit parameters is becoming more and more nervous. This paper finished a charge pump phase-locked loop system design, which is applied in a DSP clock generating system, based on the trade-offs between the circuit parameters.This paper performed the system level analysis based on the trade-offs between the loop parameters based on several normalization transfer functions of CPPLL. With the help of Matlab mathematical analysis tool, completed the amplitude frequency response and phase frequency response analysis of the normalized transfer function, and carried out a suitable system scheme for the DSP clock generating system. According to the requirements of the system scheme of each unit circuit, finished the design of the phase detector, charge pump module, voltage-controlled oscillator and frequency divider circuit in Cadence platform. At last, this paper completed the overall CPPLL circuit design and layout drawing and validation work under the SMIC 0.18 um RF process by the Virtuso tools.Finally, the CPPLL implements 1 ~ 10 times output frequency, which ranges from 25 MHZ to 350 MHZ. The peak to peak value of Cycle to Cycle jitter is less than 20 ps under DSP nominal working frequency 300 MHz. Locking time is less than 40 us. Dynamic power consumption is less than 5 mw. The current mismatch of the charge pump circuit is less than 0.1% in the output voltage range of 0.5 ~ 1.5 V. The phase noise of the voltage-controlled ring oscillator is-64.59 dBc/Hz @ 100 KHz,-91.39 dBc/Hz @1MHz and-116.55 dBc/Hz @10 MHz. PLL layout covers an area of 432× 498 um2, meeting the requirements of the DSP clock generating system. |
