Clock Duty Cycle Stabilizer On Chip Based On PLL Techniques

With advantages of Pipelined architectures, the pipelined A/D converter has been proved to be more suitable in high speed, high precision applications. To decrease the degradation of system precision, DCS (duty cycle Stabilizer) has been widely used in such application systems. As the sampling rate of A/D converter increases, clock duty cycle and jitter performance will cause the degradation of SNR, ENOB and SFDR. To achieve a higher dynamic performance of A/D converter, carefully consideration of clock duty cycle stabilization and lower jitter must be made.With the features of DLL such as synchronization between the input and output signals, equal spaced mulitiphase clocks generation and elimination of timing skew, it has been widely used in high speed high precision A/D converters as a duty cycle stabilizer.In this paper it is first studied the basic principle of phase-locked loop and delay-locked loop, including PD, CP and VCDL, second, analyzed the influence to the dynamic characteristics of A/D converter caused by clock duty cycle variation, third, studied the relationship between clock jitter performance and its limitation to SNR, SFDR and ENOB And then, a proposed DLL based clock duty cycle stabilizer for an pipelined A/D converter is presented. The required modular circuit such as PD, CP, LPF and VCDL are analyzed and carefully designed; and the essential discussion has been made.The implementation of DCS circuit is based on ASMC0.35μm-3.3/5.0V BiCMOS process. Simulation results under Cadence Spectre shows that the clock duty cycle of input clock can be adjusted from 10%~90% while the output clock duty cycle of DCS maintained 50%,and the average duty cycle error is less than 5%.The range of input clock frequency is 100MHz to 125MHz. The proposed DCS can also generate multiphase clock signals for the pipelined A/D converters. The locking time of the DLL is less than 1μs. Simulated results shows that the proposed DCS circuit can be used as a clock duty cycle stabilizer for a 125MSPS 12bit pipelined A/D converters.