Research & Design On Fast-locked High-speed And Low-jitter Clock Generator

With the development of society and economy, the growth of Mobile Internet users, Consumer Electronics is becoming more and more popular with the masses. With the rapid development of the digital signal processing technology and the improvement of the working frequency of the communication equipment and the electronic devices, the demand of the speed and precision of the clock generator is higher and higher. So the research of high speed and low jitter clock generator is of great significance.Firstly, this dissertation introduced the basic principle of the charge-pump PLL, the large signal response behavior and the linear model in locking condition. The phase noise and non-ideal effect of charge-pump PLL was analyzed and the demand of the jitter of clock generator output in ADC was concluded. So the third-order charge-pump PLL was chosen as the main circuit of the clock generator.Secondly, this dissertation introduced the working principle and the circuit structure of each module in charge-pump PLL. By using 55 nm standard CMOS process in 1.2V voltage, the design of the Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator, Loop Filter and Frequency Divider was finished. And the fast lock of clock generator was achieved by taking advantage of the reverse conducting property of MOSFET.Finally, each module in PLL and the whole loop was simulated with the analog IC design tools and the layout of the whole system was finished. The simulation results of the clock generator show that in 25℃ and nominal process corner, the RMS jitter of the 1.62 GHz output square signal of the clock generator is 2.27 ps, the locking time is 3.3μs and the total power consumption is 4.28 mW. The layout area of the clock generator is 1109*1054μm2.