High-speed Adc Clock Pulse Width Stability

High speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. Otherwise, time-interleaved ADC and multichannel-sampling technology need the special duty cycle clock to ensure their performance. So, the DCS(duty cycle stabilizer) is needed which can guarantee dynamic performance characteristics of high speed ADCs.In this paper, a duty cycle stabilizing technology that used in the clock system of high speed ADCs is thoroughly studied and a technique of minimizing the clock jitter is also investigated. With different methods of producing the duty-cycle controlling signal, the duty-cycle stabilizing techniques based on charge-pump and DLL are proposed.DLL(delay-locked loop) can generated equally spaced multiphase clocks and synchronize the output clock and the input clock. In high speed ADCs, it can be used to offer the multiphase clocks and eliminate the timing-skew. The implementation techniques of DLL and sub-circuits are investigated in this section. It is studied the PD(phase detector), CP(charge pump) and VCDL(voltage controlled delay line). Then, the false locking problem and the method of improving the locking time of DLL are investigated, methods of overcoming these problem and the correspondence circuits are presented too.The charge pump used in the DCS built on charge pump is a detector that detects the duty cycle error and produces a control voltage, which is propotinal to the duty cycle error. The duty cycle of the output signal can easily be set by controlling the ratio of the charge current to discharge current. Conventional charge pump may suffer from dynamic mismatch when changing the ratio of the charge current to discharge current.A new typle of charge pump is designed that elimilates this phenomenon. In the new circuit, the charge curret and discharge current are equal which are controlled by the output signal of the DCS. The ratio of the charge current to discharge current is set through the currents that connected to the output of the charge-pump. Another DCS is using DLL to create the non-sampling edge in order to reduce the rms-cycle jitter of the output clock. It can eliminate the harmonical locking and false locking phenomenon and speed up the locking time with the designed start-up circuit in this paper.Using DCS built on DLL, a clock circuit of 12bit-100MSPS double-sampling Pipelined ADC is designed. Except for the DCS, the clock circuit contains a 2-divider and a ciruit producing the non-overlapping clock phases. This circuit can generate 100MHz and 10% duty-cycle clock, 100MHz and 50% duty-cycle non-overlapping two phase clocks, 50MHz and 50% duty-cycle non-overlapping two phase clocks.The two DCS are implemented with the SMIC0.18μm-3.3V Si-CMOS process.The duty cycle of the output clock of the DCS built on charge pump can be adjusted from 10% to 90% in steps of 5%, the rms-cycle jitter of the falling edge is less than 5ps and the rms-cycle jitter of the rising edge is less than 28ps. The duty cycle error is less than 1%.The duty cycle of the output clock of the DCS based on DLL can be adjusted from 10% to 90% in steps 10%, the rms-cycle jitter of the falling edge is less than1ps and the rms-cycle jitter of the rising edge is less than 15ps. The duty cycle error of the 10% duty cycle clock is less than 3% and the duty cycle error of the 50%⁹0% duty cycle clocks is less than 1%. The lock time of the DLL is about 300ns.Simulated with the double-sampling S/H circuit and the 1^st sub-ADC, the clock circuit fulfills the requirements of the 12bit-100MSPS double-sampling Pipelined ADC.