Design Of A 2.5GHz PLL Clock Generator

With the rapid development of electronic information industry, electronic information industry as the core technology of microelectronics technology also got rapid development. Modern electronic systems require more stable frequency source, PLL frequency synthesizer is increasingly becoming an integral module of IC systems. For more and more demand of communication systems and microprocessor systems, designing high-performance PLL clock generator is a very difficult challenge under the conditions of high-speed with 2.5GHz, low supply voltage with 1.2V.This thesis applied for high speed communication interface chip clock generator as the starting point , based on the analysis of the basic principles and the mathematical model of charge pump PLL , implements the system-level parameters design and establishes the system simulation model, Matlab System Simulation results show that the system parameters meet the design specifications.For harsh conditions of low supply voltage with 1.2V and high speed with 2.5GHz, this paper focus on improving the noise performance, power performance and circuit speed of PLL, carry out the work of high-performance fractional-type phase-locked loop clock generator design. Main tasks: First, design a fully symmetrical output signal timing, high-speed phase frequency detector and high-current matching wide-swing output fully differential charge pump circuit. Based on the traditional single-ended charge pump, improve the design with a wide swing current source. To further eliminate the non-ideal factors, improve the single-ended charge pump structure to differential, the differential output voltage swing is 1.2V, the current mismatch is less than 34nA, the control voltage error is less than 5mV. Secondly, through the digitally controlled switched-capacitor array capacitance to extend the tuning range of LC-VCO, simulation results show that the oscillator output frequency range covers the range from 4.5GHz to 5.5GHz, the phase noise is-112db @ 1MHz. Finally, through the current-mode logic circuit to achieve a high-speed multi-mode programmable frequency divider, the prescaler ratio is continuously adjustable from 64 to 127. To overcome the problem of power consumption in current-mode logic circuit , through an optimized large-signal theory design methods of power and speed, this divider consumes only 20.4mW.PLL clock generator circuit was fabricated on Chartered 0.13μm CMOS Generic Analog/ RF technology, Hspice overall transient simulation results show that the lock time is less than 50μS, 2.5GHz four-phase quadrature output clock signal cycle to cycle jitter rms value is 1.2268ps, peak to peak value is 6.4172ps, all of which meet the design specifications.