Research On Time-to-Digital Converter For All-Digital Phase-Locked Loop Application

In the field of RF wireless communications, traditional frequency synthesizers mostly utilize charge pump phase-locked loops. The use of low-voltage deep-submicron CMOS processes allows for an unprecedented degree of scaling and integration in digital circuitry, but complicates implementation of traditional RF circuits. Recently All-Digital phase-locked loop (ADPLL) have been an hot topic due to its good scalability, programmability and robustness.Time-to-Digital Converter(TDC) is a key building block in ADPLL, TDC resolution dominates ADPLL in-band phase noise. In this thesis, the main work is research and design a time-to-digital which can be applied in 2.5-5GHz wideband ADPLL. The research features are:1. During and after the acquisition of PLL lock, PLL’s requirement of TDC’s detectable range and resolution is different. During the acquisition, the PLL requires TDC has large detectable range. After the acquisition of PLL lock, the TDC should have high resolution. To meet the different requirements of different PLL status, the designed TDC has two operation modes, coarse mode and fine mode, Mode-Arbiter can choose the mode automatically according to the amplitude of TDC’s input singnal.2. Since the PLL is Franctional-N PLL, after the acqusion of PLL lock, the changing divide ratio increase the amplitude of TDC input. To enlarge the detectable range of fine mode, ensure that the TDC always work in fine mode after the PLL is locked, the TDC quantization unit utilizes 1-bit decision-select as its first stage and Vernier gated-ring-oscillator(Vernier GRO) as its second stage.3. Using SR flip-flop as comparator in conventional Vernier GRO limits the detetable range and the design flexibility of GRO. In this design, using a new structure phase comparator eliminates the limitation to detectable range and improves the design flexibility of GRO.The time-to-digital converter is implemented in TSMC 0.13μm with 1.2V power supply. Measurement results shows that the TDC’s sampling rate is not lower than 40MHz, the detectable range of coarse mode is not smaller than 25ns, fine mode range is 1.8ns. When applied in ADPLL, the in-band phase noise in 3.68GHz is-92dBc/Hz@5kHz, corresponding a 23 ps effective resolution.