Research And Design Of Time To Digital Converter For All Digital Phase Locked Loop

Time-to-Digital Converter(TDC)is a time measurement circuit that converts successive time-domain signal into digital signal and is first used in high-energy physics.With the development of semiconductor technology,TDC performance has been improved qualitatively,the resolution can reach the picosecond level,and gradually applied to all-digital phase-locked loop(ADPLL)and analog-to-digital converter(ADC).In the ADPLL loop,the time-to-digital converter(TDC)is mainly used to replace the traditional phase-locked loop in the charge pump and phase detector,it is the primary symbol to distinguishe ADPLL from the traditional PLL.The resolution of TDC directly affects the level of phase noise in ADPLL,so the purpose of this paper is to design a high-resolution time-to-digital converter.This paper first introduces the basic principle of TDC,analyzes the structure of various TDC circuits,and points out the advantages and disadvantages of different structure TDC.The loop frequency response model is constructed,and the influence of TDC resolution on phase noise of ADPLL is theoretically analyzed.In order to meet the performance requirements of ADPLL for high-resolution TDC,it is proposed to use coarse-fine TDC structure,through the coarse quantization unit and the fine-grained unit to achieve a large measurable range and a higher resolution.The paper mainly designs the delayed chain TDC and the negative exponential TDC,improves the 2x time interval amplifier and the digital self-calibration unit.As the analog circuit is susceptible to the influence of the external environment,the digitization of the circuit becomes the direction of the development of the integrated circuit.In this paper,the random interpolation type TDC which can be digital synthesizable is proposed.Based on the mathematical statistics principle,it can effectively avoid the circuit mismatch and the external noise to cause the linearity error.This resolution of this structure TDC has nothing to do with the size of mos tube which can effectively reduce the circuit area,the circuit contains only a delay unit and the accumulator,the circuit structure is simple,can achieve high resolution.Based on the 0.18?m CMOS process,the tube-level circuit of the two-stage mechanism TDC is built and simulated.The power supply voltage is 1.8v and its resolution is 970 fs,and the dynamic range is 2.309 ns.The linearity of the delayed chain TDC,DNL is -0.15 LSB,INL-0.18 LSB,are less than 1LSB.Based on the 0.18?m CMOS process,the TDC using stochastic phase of N =9 is built and simulated.When the input clock period is 5ns,the output differs from the theoretical value by-4LSB.For TDC using stochastic phase at N=14,the circuit design and behavior level simulation with verilog is carried out.When the input clock period is 1ns,its resolution is about 977 fs.