The Research And Design Of A Fast-locking All Digital Phase-locked Loop

Phase-locked loop(PLL:Phase-locked Loop)is a key module to realize digital signal synchronization.It uses feedback control principle to maintain a certain relationship between the phase and frequency of the output signal and the input signal.Since being proposed,PLL has been widely used in many fields such as integrated circuit design and wireless communication.Furthermore,it has been implemented a lot in application-specific integrated circuit design such as data clock recovery circuits and frequency synthesis circuits.In recent years,5G and the Internet of Things have been leading the wave of technology,and the important role of PLL has become more prominent.New application scenarios place new requirements on the PLL.In the past ten years,the All Digital Phase-locked Loop(ADPLL)has gradually become a rising star in the phase-locked loop.With the advantages of adaptation to advanced digital signal processing technology,compatibility with low-voltage processes,and a good support for process upgrade and migration,ADPLL has attracted extensive attention from the research community and has developed rapidly.Contemporary wireless communication has strict requirements for data real-time,which makes fast locking an important subject in the field of phase-locked loops.This thesis researches and designs an all-digital phase-locked loop circuit that can achieve fast lock.In order to achieve fast locking,this thesis proposes a phase detection algorithm and locking algorithm based on phase domain calculation of an all-digital phase-locked loop innovatively.The differential phase detection relation of the new phase detection algorithm proposed is derived from the traditional algorithm,and the locking algorithm is proposed based on a new dynamic step adjustment strategy through further mathematical derivation and result analysis.These measures increase the system's locking speed by nearly 70%.At the same time,in order to match the requirements of time measurement in the new algorithm,this thesis uses the behavior-level modeling results as a reference and guidance,and adopts a dual dynamic range time-to-digital converter structure.In this structure,by selecting an appropriate clock strategy and time resolution,a long time interval(generally tens of nanoseconds)can be measured,and a certain measurement accuracy is guaranteed.In addition,this thesis proposes a new code word control method for digitally controlled ring oscillators.On the same structure of the conventional digitally controlled ring oscillator,the new method can generate more resonance frequencies,and has a higher frequency resolution in the case that the resonance frequency range is consistent with the traditional.The fast-locking all-digital phase-locked loop circuit designed in this thesis is based on a 40nm CMOS process.Under the working environment of 1.2V power supply,the lock time of the circuit is less than 10 microseconds,and it provides a tuning range of 0.6-2.1 GHz.The output signal has a period jitter of less than 25ps and supports fractional frequency division.