Design Of Low Phase Noise CMOS Digital Phase-locked Loop

With the rapid development of modern electronic technology and the continuous improvement of the sensitivity of communication system,the requirement of phase noise is more and more strict.Lower phase noise means higher signal-to-noise ratio and lower bit error rate.Meanwhile,with the development of Moore's Law,higher requirements for circuit integration make it easier for digital phase-locked loop to reduce the required chip size in advanced CMOS process than analog phase-locked loop,and become an attractive alternative to analog phase-locked loop in the design of frequency synthesizers and clock data recovery circuits.As digital phase-locked loop is a system with limited information precision,the phase noise of digital phase-locked loop is usually worse than that of analog phase-locked loop due to quantization error.Therefore,how to improve the noise performance of digital phase-locked loop has been a research focus.A low noise phase locked loop based on ring oscillator is studied and designed in this thesis.To achieve lower out-of-band noise,a feedforward ring oscillator is used as the Digitally Controlled Oscillator(DCO),allowing the oscillator to achieve lower phase noise for the same amount of power consumption.For in-band noise,a Time-to-Digital Converter(TDC)based on RC delay chain is designed.The RC structure composed of metal wire resistance and transistor gate capacitance is used to achieve a time resolution of about 300 fs by taking advantage of their very small time constant.The input jitter introduced was about 97 fs,less than the jitter of the reference frequency.Secondly,pulse width modulation is introduced into the digital filter.By increasing the proportional control coefficient and reducing the enabling time,the proportional path gain remains unchanged and the quantization noise converted to the input is reduced.This thesis is based on TSMC65 nm CMOS technology,using Cadence IC617 platform to complete the schematic and layout design and post-simulation.The power supply voltage is 1V and the input reference frequency is 200 MHz.The simulation results show that the locking time of PLL is close to 70?s,the integrated noise of phase noise from1 k Hz to 100 MHz is-49.98 d Bc,the root mean square jitter is 178.4fs,and the total power consumption is 6.61 m W.