Research On Key Technologies Of Ku-Band Hybrid Structure Frequency Synthesizer

Phase-locked loop frequency synthesizer as a clock generation circuit can generate accurate frequency signals and is a key module in radio frequency communication systems.With the development of semiconductor technology and the depth of research,people have put forward more stringent requirements on the output frequency range,phase noise,stability,integration,and power consu,ption of the PLL system Therefore,the hybrid structure PLL combining the advantages of digital phase locked loop and analog phase locked loop has received more and more research and attention.This thesis focuses on the research and design of a Ku-band analog-digital hybrid frequency synthesizer,and proposes a digital-analog hybrid phase-locked loop based on a Time-to-Digital Converter(TDC).This structure adopts a multi-phase ring oscillator that is injected and locked by a Digitally Controlled Oscillator(DCO)as the TDC.Because of the injection locking,the quantization step of the TDC automatically tracks the output cycle of the DCO.And when the output frequency of the DCO changes due to temperature,power supply voltage,etc.,the cycle of the ring oscillator will also follow a synchronous change,so the minimum resolution of the TDC and the output of the DCO will be an exact proportional relationship,not affected by temperature,voltage,No additional calibration circuit is required.This thesis first introduces the working principle of the hybrid structure PLL and analyzes the loop model.Then introduce the structure of common TDC,analyze its main performance indicators.Then the specific implementation method of TDC in this paper is proposed.In order to further improve the quantization accuracy of TDC,cross-coupling resistance is used to double the phase number of output ring oscillator.The current-vector method was used to analyze the frequency-locked range of the injection-locked ring oscillator,the influence of injection locking on the DNL,and the effect of injection locking on the phase noise.When the ring oscillator is injected and locked,the noise is due to the DCO oscillation signal with good noise performance.Suppress noise.Finally,analyze and design the,ain modules of the remaining PLLs.The numerically controlled oscillator uses a CMOS cross-coupled LC oscillator to increase the output frequency tuning range through a configurable switched-capacitor array.The digital signal is converted into analog voltage by an analog-to-digital converter.In order to count across the clock domain,an asynchronous high-speed counter composed of an asynchronous frequency dividing circuit can accurately count the integer period value of the output signal of the numerically controlled oscillator.This thesis is based on TSMC 65nm CMOS process,using Cadence platform to complete the design and layout.With a 1.2V supply voltage,the input reference clock frequency is 40MHz.The simulation results show that the phase-locked loop frequency locking range is 13.4-15.2GHz.Within the frequency locked range,the loop locking time is less than 10us;the phase-locked lbop has a phase noise of-106.3dBc/Hz at a frequency offset of 1MHz.The phase noise is-128.3dBc/Hz at a frequency offset of 10MHz,and the TDC resolution is less than 9 ps.The total power consumption of the system is 32.4mW.The area of the chip without the PAD is 482 ?m×302 ?m.