Research Of 10-bit Low Power Successive-approximation Analog-to-Digital Converter

With the improvement of integrated circuit,So C(System-on-Chip)will be the future direction of the development.The analog-to-digital converter,as an interface of the analog circuit and digital circuit,it has an important impact on the performance of the system.Successive approximation analog-to-digital converter(SAR ADC)is a common analog-to-digital conversion architecture.Because of its simple structure,low power cons?mption and smaller area,compared with the same precision sigma-delta ADC or high-speed Flash ADC,can achieve a reasonable compromise between speed and precision.With the continuous progress of CMOS technology,sampling rate is also rising,and now has been able to reach the GHz level.SAR ADC has a great prospect for development.Based on the analysis of the principle and power cons?mption of traditional successive approximation ADC,a new low power SAR ADC circuit structure is designed.In order to achieve high speed and low power cons?mption,this article adopts asynchronous sequential logic control structure.The sample and hold circuit is designed based on the Miller capacitor,which reduces the charge injection effect and the clock feed-through effect.The comparator adopts the dynamic pre-amplifier structure,which eliminates the static power cons?mption and meets the low power cons?mption design requirements.DAC of segmented capacitor structure,in the monotonic switching to the GND timing,do a partial pull processing,reduce the common-mode voltage changes,ease the comparator DC offset.SAR logic circuit using window-type circuit instead of the traditional shift register structure,the output directly connected with the DAC and the latch,speed and power are optimized.In the case where the input signal is 1MHz sine wave and sampling frequency is 20 MHz,the simulated SNDR is 57.14 d B,SFDR is 63.18 d B,DNL and INL are 0.43 LSB and 0.32 LSB.The overall power cons?mption of the circuit is 523?W.Fo M is 44.5f J/conv.The performance basically meets the design requirements.Through the simulation of SAR ADC circuit,the feasibility of low power SAR ADC structure and logic control is verified.