Research Of A 12bit High-speed Low-power Sar ADC Based On A Two-step Structure

With the rapid development of the communications industry, information technology, engineering, intelligent, analog to digital converter(ADC) module as the key to get through the data acquisition, processing, feedback and other industries, it is required to have high-speed, low-power performance. In this trend, some traditional ADC architecture can not meet the higher performance requirements of the corresponding shortcomings exposed. Therefore, the analysis of the advantages and disadvantages of the traditional structure and new hybrid ADC, a 12-bit 50MS/s high-speed low-power successive approximation ADC working at 1.2V supply voltage based on two-step structure was proposed in this thesis.Firstly, to the power consumption of SAR ADC, the comparator can be more optimized power consumption from the SAR ADC’s DAC, comparator, SAR digital logic power consumption in three parts. The power consumption of comparator occupies most in the three parts power consumption of DAC, comparator, SAR digital logic, if use conventional SAR ADC structure to achieve high-speed 50MS/s high-precision 12 bit SAR ADC. Because the high-precision comparator uses traditional structure of pre-amplifier+latch, high-speed response requiring pre-amplifier current very large. This paper proposes the use of coarse and fine comparators theory, using low-power coarse comparator in high bits quantization, using high-power fine comparator in the low bits quantization.Secondly, to the speed of SAR ADC, for the capacitors of DAC settling time constraint SAR ADC’s speed, the popular new hybrid ADC(two-step ADC) has been proposed in this work. However, Pipeline+SAR structure as the typically structure of high-speed low-power two-step ADC, has shortcomings like needing Complex circuit structure, requiring digital background correction and so on. This work proposes a two-step structure using both coarse and fine SAR ADC, which using segmented capacitor array of the coarse SAR ADC to decrease the high bit capacitance value achieve high speed, and using time sharing establishment to establish the capacitor array of the fine SAR ADC. This approach is the core technology of this article.Thirdly, use Matlab modeling to verify the behavior correctness of the two-step ADC structure mentioned in this work. Some circuit structure solutions such as capacitor redundancy correction, capacitor weight correction and offset voltage correction have been proposed to solve the non-ideal factors impacting the ADC performance, which added in the Matlab modeling.Finally, based on 55 nm CMOS process, this work completed the key circuits as well as the overall two-step ADC performance simulation. In order to better conform with actual results, key circuits and key nodes are added parasitic parameters in the process of simulation. The simulation results indicated that with a sampling frequency of 50MS/s, ADC’s spurious free dynamic range SFDR is 81.93 dB, the signal to noise and distortion ratio SNDR of 72.62 dB, effective number of bits ENOB is 11.77 bits. The total power consumption is 3.16 mW at the power supply voltage of 1.2V, FoM value is 18.1fJ/Conv. The performance meet the high-speed low-power design requirements.