Design Of 12-bit Advanced Low-power Algorithm Analog-to-digital Converter

The entire semiconductor industry is developing,and the analog-to-digital converter is an important part of communications,video transmission,and other fields.The accuracy and speed of ADCs are also becoming higher with today's development.Among many ADC structures,the algorithm ADC has the design advantages of high precision,low power consumption,and low cost.So this thesis has carried on relevant research to 12-bit highprecision low-power algorithm ADC.Firstly,The thesis introduces the research background and research significance of this subject and analyzes the basic characteristics of the ADC algorithm;secondly,it uses Redundant Signed Digit coding(RSD code)to improve the traditional algorithm ADC.The algorithm ADC depends less on the performance of the comparator,which also improves the accuracy of the algorithm ADC and reduces the power consumption.At the same time,the algorithm ADC is also modeled by Matlab/Simulink,which fully verifies the rationality and effectiveness of the algorithm ADC using RSD encoding.And summarized the error sources that affect the accuracy of the algorithm ADC;then the principle analysis and simulation of the various circuit modules of the algorithm ADC,including the introduction and principle analysis of the capacitor array,the bandgap circuit,the op-amp circuit,and the nonoverlapped clock circuit,CMOS transmission gate circuit and bootstrap circuit,adder circuit,a comparator circuit,voltage regulator circuit,mux-input circuit,and bias circuit,and finally the overall circuit.The simulation under the three process corners of tt,ss,and ff,as well as the layout and drawing of the layout.Its advantages(1?3)and innovation points(4?6)are:1.The RSD encoding mode greatly improves the threshold error limit of the comparator used by the algorithm ADC.This approach improves the accuracy of the algorithm ADC and reduces the design difficulty.2.The time division multiplexing function of the capacitor reduces the layout area and reduces the power consumption.3.The algorithm ADC uses a fully differential architecture to suppress common-mode disturbances and improve the quantization range and accuracy.4.The compensation capacitor in the capacitor array compensates for the offset voltage at the input end of the op-amp,which increases the accuracy of the algorithm ADC.5.Algorithm ADC has a mux-input interface,which is easy to integrate into other chips as a single module.6.The comparison circuit uses a combination of a fully differential switched-capacitor adder and a comparator,which avoids the use of negative voltages on the chip.Finally,a design based on DBH 0.18?m CMOS process,using 1.5 bit/level high-precision low-power arithmetic ADC,its sampling frequency is 0.5MHz,power consumption is 6mW,ENOB is 12 it,layout area It is 300?m*650?m.