Design Of 9-bit Low-power Successive Approximation Analog-to-digital Converter

With the development of science and technology,people have to process more and more signals.Compared with analog signals,digital signal processing is more efficient and faster.However,the real world is basically analog signals.At this time,analog-to-digital converters are needed to convert analog signals.Convert to digital signal.Digital-to-analog conversion is a bridge between digital signal and analog signal conversion.Among them,SAR ADC is widely used in various biomedical and wireless communications because of its low power consumption and small area.This article will mainly design a low power consumption 9-bit successive approximation digital-to-analog converter.The main work of the thesis includes the following:1.On the basis of in-depth study of the SAR ADC parameter characteristics and detailed comparison and analysis of the ADC circuit structure of different structures,the SAR ADC system design,including the optimization design of timing and noise,has been completed.2.Based on TSMC 0.18um 1.8V CMOS process,completed a 9bit 320KHz low-power semi-synchronous SAR ADC circuit design and simulation verification,including comparators,DAC arrays,SAR logic timing,bootstrap switches,and digital switches design.Aiming at the design requirements of low power consumption and small area,the paper optimizes the design of(1_CM-based switching timing and dummy capacitor multiplexing DAC array,reducing the number of total capacitors,thereby reducing the power consumption and area of the circuit;adopting semi-synchronous The time sequence reduces the delay of the redundant comparator and improves the circuit speed.The circuit simulation result shows that:under 1.8V power supply,the ADC power consumption is within 10u W at a speed of320KS/s.The effective number of bits is 8.9 bits,INL is 0.33LSB,DNL is 0.26LSB,SNR is55.8d B,and SDNR is 55.6d B.Meet the design requirements.3.Completed the layout design and simulation verification of SAR ADC,focusing on the optimized design of the comparator layout and the DAC array capacitance matching layout,using a common centroid symmetric structure to achieve the expected results.The layout simulation results show that the DNL of the SAR ADC is 0.49LSB and INL is 0.86LSB,which meets the design requirements.4.Completed the SAR ADC tape-out test.The chip test results show that the effective number of bits is 8.12,the INL is 1.3LSB,the DNL is 0.4LSB,the SNR is 51.6d B,and the SDNR is 50.6 when the sampling speed is 320KS/s.d B.By comparison,the final measured results are slightly better than the design goals.This is within the acceptable range and meets the design requirements.