Design And Analysis Of Phase-Locked Loop

With the continuous development of integrated circuits, the rise of internet of things, high performance and low cost of SOC has become the focal point of design on integrated circuits. PLL is the main clock generator for SOC and its design has become very critical. This paper is dedicated to provide clock generator for a particular DSP chip, which used in digital signal processor (DSP) clock system that provide stability and accurate clock signal for DSP chip .This paper firstly introduces the structure and theory of phase lock loop, and focuses on the analysis of the composing principle for the charge pump phase-locked loop. Then the text analyzes the function, the mathematical model and transmission function of each module in charge pump phase-locked loop. These modules include phase frequency detector, charge pump, loop filter, voltage control oscillator and separate frequency device. In these basis, it establishs phase-locked loop system modeling on system, establishing transmission function, observing the zero pole distribution, analyzing the influence of frequency response and noise. According to the charge pump phase-locked loop theory, Verilog - A model was established for charge pump phase-locked loop, achieved charge pump phase-locked loop function in behavioral level .In PLL circuit implementation, this paper discusses the traditional structure and phase lock loop function module deficiency, and puts forward the corresponding improvement scheme that contain three major innovations. One is put forward with switch accelerated functions and the charging and discharging current adjustable charge pump. Another is proposed with RS flip-flops differential delay unit. The third is converting the single coefficient frequency divider into programmable coefficient one. Dead zone is involved in traditional phase frequency detector, this article designed a dynamic phase frequency detector without dead zone, having reduced the blind range, and speed, area and power are more superior than traditional phase frequency detector . Because of the nonideal factors, traditional charge pump behaviors bad. This paper proposes the switch accelerated functions and the charging and discharging current adjustable charge pump, not only are the charging and discharging current more matching, also prevent well the charge injection, clock feed through effect and charge sharing effect. It also adapted to the requirements of separate frequency coefficients, and compensated the impact of circuit caused by not ideal factors on process manufacturing process.Then it helps to improve the stability of phase-locked loop and product yield. As the limited of the traditional vco delay unit swing amplitude, this paper puts forward with RS flip-flops differential delay unit that sensitivity, flip speed, static power consumption and resisting noise performance has been improved. As traditional phase lock loop use the frequency divider with fixed points frequency coefficients, this paper presents a programmable frequency divider with dividing frequency coefficients programmable. Arbitrary value between 2 ~ 16 can be selected thus different clock frequencies which suppled by phase lock loop are prepared for DSP chip.Layout uses SMIC 0.18μm CMOS Mix-Mode 1P4M process, 1.8 V power supply and the whole territory area is 168μm×160μm.In Cadence environment, use spectre software simulation, the results show that the charge pump phase-locked loop can realize 10MHz ~ 160MHz capture range. When output frequency of vco is 160MHz, loop of locking time is 4us, power consumption is 1.368 mW ,the jitter is 70ps. To sum up, the pll can completely satisfy DSP chip to the clock signal requirements.