A Multiplying Delayed Phase-locked Loop With Low Jitter And Uniform Phase Separation

With the rapid development of wireless communication technology,the requirements for integrated circuits are increasing.In infrared laser ranging imaging technology,time to digital converter(TDC)is usually used for quantitative counting measurement.As the core driving module of TDC,the clock system puts forward higher requirements on its performance such as jitter,frequency,phase split uniformity,and duty cycle.As a new clock structure,Multiply-Delay Loop Locked Circuit(MDLL)combines the working mechanism of delay-locked loop(DLL)and phase-locked loop(PLL),so it has the advantages of frequency multiplication and low jitter which can be well applied in TDC system.In this paper,the internal connection and difference between MDLL,DLL and PLL are studied from the perspective of locking characteristics,phase adjustment characteristics and jitter accumulation mechanism.The influence mechanism of phase realignment error on the jitter accumulation of the MDLL is also analyzed,and the overall strategy of low jitter MDLL design based on offset suppression is proposed.Based on the theoretical basis and application requirements,this paper designs a MDLL with low jitter and uniform phase separation.The system controls the frequency doubling process and mode switching through the upper loop,and the lower loop implements the reference clock injection calibration and phase locking process.The logic selector with transistor switch control method replaces the traditional logic gate control method,which increases the upper limit output frequency and frequency multiplication of the system;An improved phase detector structure is designed to realize phase-ondemand detection,eliminating the delay interference of the frequency divider module in the phase-detection feedback loop,and ensuring the basic alignment of the reference clock injection signal and the output feedback signal.A reference clock injection calibration technique that can suppress static phase offset is proposed.By amplifying the static phase difference at the input of the phase detected,the charge pump can continue to respond to adjustment under a smaller phase deviation,which can reduce the static phase offset after locking effectively,and finally achieve the accurate injection of the reference clock.Based on the TSMC 0.35?m standard CMOS process,the Cadence EDA software design tool has been used to complete the circuit design,layout design and system front-end simulation verification of the MDLL.The chip test results show that the MDLL function is normal,with 8 uniform split-phase output signals.The maximum splitphase uniformity deviation is 45 ° ± 3.47 °.The ratio of the output clock duty cycle is 52.06%.The output frequency of MDLL is 320 MHz.When the static phase offset elimination module is off,the peak-to-peak jitter of the output clock is 89.9ps,and the root mean square jitter is 18.5ps.After the static phase offset elimination module is turned on,the system completes the reference clock injection calibration.The peak-to-peak jitter is reduced to 25.4ps,and the rms jitter is reduced to 3.17 ps.The consistency of multi-chip test performance is good,and the total power consumption of the chip is about 86 m W.All performances are degraded compared with the simulation results,but meet the design requirements basically,which can meet the application requirements of array TDC.