Research And Design Of Key Units Of The Pipelined ADC Based On 40nm Process

The latest Intel processor adopts the current relatively advanced 14nm technology. However, the technologies adopted in domestic chips still remain in the stage of 0.13um and 0.18um. Compared with big companies like TI, the level of domestic ADC chips is relatively low. And the market is almost monopolized by foreign companies.The level of domestic chip urgent need to enhance.In this thesis, the author firstly calculated and deduced key units of pipelined analog-to-digit converter, including calculating requirements of operational amplifiers, confirming sampling capacitances analyzing and comparing sampling circuits with three structures. Later, using the modeling tool, Matlab, the author completed the modeling work of the pipelined analog-to-digit converter. It not only clarified indicators in every module, but also laid the foundation for future study pertaining to the influence of certain specific non-ideal factor on the whole performance.In this thesis, the author has designed operational amplifiers with two structures to meet the demand of the pipelined analog-to-digit converter. Due to factors such as the lower supply voltage under the 40nm technology, the higher grain demand of operational amplifiers, the power dissipation and others, overall, operational amplifiers adopted the folded-cascode structure, post simulation results were as follows. The Gain was 80.41dB. The GBW was 759.6MHz. The PM was 61.1°. The power consumption was 7.2578mW. As far as handling non-ideal factors were concerned, the author mainly studied on two aspects-the capacitor mismatch and the nonlinear resistance of the switch. In order to reduce the nonlinear resistance of the switch, the author designed the bootstrap switch to take place of the common switch and analyzed the effects before and after the bootstrap switch is used.Combining with other modules, the author finally completed designing the 12bit/60Msps pipelined analog-to-digit converter based on the SMIC 40nm CMOS process. The results of the single channel were as follows. The SNDR was 68.7dB. The THD was-75.1dB. The SFDR was 74.6dB. The ENOB reached 11.12bit. And the power consumption was 61.9mW.