Clock And Data Recovery Circuit Design Based PLL

With the exponential growth of the number of Internet nodes, the volume of the data transported by its back-bone continues to rise rapidly. The load of the global Internet back-bone is expected to as high as 11Tb/s by the year 2005, indicating that the required bandwidth must increase by a factor of 50 to 100 every seven years.Among the available transmission media, optical fibers have the highest bandwidth with lowest loss, severing as an attractive solution for the Internet back-bone. However the electronic interface proves to be the bottleneck in designing high-speed optical systems. In order to push the speed of operation beyond the capabilities of the fabrication processes, a number of transceiver can be fabricated on the same chip. The clock and data recovery (CDR) circuit is a key component in the optical communication system as well as many other high-speed serial data communication systems, and is the main bottleneck of systems'upgrading to higher speed.This dissertation describes the design of a PLL based frequency acquisition aided dual-loop CDR, which is based on the standard SMIC0.18μm mix signal CMOS technology. A linear phase detector (PD) is introduced that compares the phase of the incoming data with that of a half-rate clock. A half rate Digital Quadricorrelator Frequency Detector (DQFD) is designed to compare the frequency between pseudorandom data and the clock. The paper also incorporates a four-stage ring oscillator to achieve a wide tuning range. At the end design a differential charge pump with positive feedback, which have high speed and low power consumption, the charge pump have only NMOS that improves the match between up current and down current. The circuit achieves a peak-to-peak jitter of 34.6ps with a pseudorandom sequence, while dissipating is 68mW from 1.8 supply.According to the simulation results, this CDR circuit can work on 2.5Gbps stably and meet the corresponding ITU-T recommendations.