Analysis And Design Of A CMOS Charge Pump PLL

In today’s society, electronic products swept the world, the Phase Locked Loop(PLL) which is an important part of electronic products, has been used in various fieldsof life. As so its performance is crucial.After study of a large number of reference material, this paper first give a briefintroduction to the development and application of PLL. Especially the domesticdevelopment situation and future trend of phase locked loop were introduced.Then the basic structure and working principle of phase locked loop were introduced,too.Through the mathematical modeling of charge pump phase locked loop for each module,including frequency phase detector, charge pump, a low pass filter,voltage controlledoscillator and a frequency divider modeling. On this basis of charge pump phase lockedloop of power consumption, noise, tracking performance, capture performance andstability has been analyzed, this paper proposed the methods of noise suppression.In order to get PLL’s performance better, the paper chose Charge Pump PhaseLocked Loop (CPPLL) structure for study. One chapter was used to introduce the fiveimportant parts of CPPLL, include Phase Frequency Detector(PFD), Charge Pump(CP),Loop Oscillator(LO), Voltage Controlled Oscillator(VCO) and divider, their workingprinciples characteristics and typical circuits are introduced. Then through the analysisof various performance, we ultimately select the ideal performance of the improvedcircuit block.Circuit simulation is carried out by Cadence and Spice. In this paper, after a largenumber of calculations and simulations, components were selected as precharged phasefrequency detector,32divider, second order loop filter and voltage controlled oscillatorconstituted by a differential pair. Working voltage is3V, when the reference frequency is20MHz, the output frequency reaches640MHz. And achieve a lock in6μm. The finalsimulation results verify our theoretical analysis.