Design And Analysis Of The Clock Mesh

With the development of integrated circuit technology, the process feature sizescontinue to shrink, the integration and frequency of chip is enhanced, making therequirements for the design of clock network higher than ever before. Clock mesh is akind of net-shaped clock network, characterized by low clock skew, small OCV, andstrong driving capability, fit for chip design which has strict demand on clock network.However, the clock mesh has very special structure as it uses multi-driver to drive theglobal mesh, and then uses the global mesh to drive all loading sinks. The structureleads to two problems in designing clock mesh.On one hand, the clock mesh design is more difficulty. The support of EDA toolsis imperfect, cannot be automatically, usually by hand to achieve, time consuming andthe designing need depending heavily on the experience of designers.On the other hand, the structure results in the inaccurate calculation of delay ofclock mesh, for the cell delay model based of voltage source cannot calculate the delayof multi-driver.In order to solve the problems above, this paper deeply explores clock mesh, and itincludes the following main contribution and innovation.Firstly, it gives a detailed analysis of the clock mesh. Usually, the clock meshconsists of Top Chain, Global Mesh, and Local Tree, among which Global Mesh is thekey part of clock mesh design. As a result, it is of guiding significance to have a deepunderstand of the structure of clock mesh.Secondly, usually clock grid can only be manually designed by experienceddesigners, when the modification of the design module, the clock grid often needs tore-design. This article explores a method of automatically by the EDI tool, combinedwith the structural characteristics of the clock mesh, the topology of placement andclock structure, the type of the clock mesh is fixed. Then, design specificationdocuments to guide the tool to complete the design of the clock grid, reduces theiteration time and the difficulty of design. By adoption of clock mesh, the design bringsout local clock skew as little as26.4ps while the number reach43.5ps with the sue ofclock tree.Finally, as for the problem of incapability to calculate the delay of multi-driver,can only be estimated, the accuracy is difficult to guarantee. This paper obtains theinterconnect parameters of clock mesh through parasitic extraction tool. It also usesHspice tool to simulate and obtains the delaying information of clock mesh, which isback-annotated to EDA tool to guide timing analysis. Through the process, the delayinformation of multi-driver is obtained and the trouble of analyzing clock mesh inphysical design is completely got rid of. This paper studies two difficult problems existing in the design of clock mesh, thusproviding powerful support to realize the clock mesh design in engineering practice.