Research On Reconfigurable Wideband Frequency Synthesizer Based On All-Digital Phase-Locked Loop

Research about all-digital phase-locked loop (ADPLL) is becoming an attractive topic, because it is compatible with scaling of CMOS technology and is easily reconfigurable.Firstly, linear mathematical model and phase noise model are established in system level. Loop parameters, dynamic characteristics and issues of spurs are also discussed. A loop tracking controller is proposed, which can shorten the locking time.Discussion of circuits design is presented in detail, including wideband digitally controlled oscillators (DCO), current-mode logic dividers, multiplexer, dynamic divider and automatic frequency calibration (AFC). Oscillators covering2.5-5GHz bands are desired in this frequency synthesizer architecture, with total tuning range of67%. It is feasible and reasonable to employ two sub DCOs. The all-digtal automatic frequency calibration is based on variable phase accumulator and time-to-digital converter, which works faster compared with analog AFC.A novel varactor using single PMOS or NMOS is proposed to realize finer frequency resolution without an extra fixed capacitance. The varactor utilizes the capacitance difference of one MOS between the saturation and linear region.This work is designed in TSMC0.13p.m CMOS technology. Measurement results show that the total tuning range of two DCOs are2.4-5.25GHz. HB DCO has a tuning range of3.44-5.25GHz (41.6%), and LB DCO has a tuning range of2.4-3.86GHz (47.4%). The synthesizer output frequency is0.6-2.62GHz. The measured phase noise achieves less than-119.3dBc/Hz. By employing the proposed PMOS varactor, the measured minimum frequency resolution is18.5kHz around2.4GHz output. The proposed varactor can improve frequency resolution by more than50%, compared with the minimum-sized inversion-mode varactor.