Research And Design On CMOS Mm-Wave Wideband Frequency Synthesizer

The traditional wireless communication systems have been difficult to meet the demands of the future wireless communications.Hence there has been a growing requirement for researching in the fifth generation(5G)wireless communication systems.Due to its rich spectrums,millimeter wave has become a good choice for the 5G wireless communication.According to the research results of the 5G bands,this paper presents an integer-N charge pump phase-locked loop frequency synthesizer which can provide 44GHz~58GHz and 22GHz~29GHz orthogonal local oscillator signals.Based on the direct-conversion(DC)and sliding-IF heterodyne(SIH)transceiver architectures,this frequency synthesizer can be suitable for the whole preliminary 5G frequency bands communication systems proposed by International Mobile Telecommunications and the Ministry of Industry and Information Technology of the People's Republic of China.The main research contents and results are as follows:1.According to the performances of the recently published state-of-the-art mm-wave frequency synthesizers and wideband VCOs,the target performances of the mm-wave wideband quadrature frequency synthesizer in this paper are formulated as: the phase noise is less than-90 d Bc/Hz@1MHz and-115 d Bc/Hz@10MHz,the reference spurs is less than-60 d Bc,the quadrature phase error is less than 3o,and the locking time is less than 6?s.In addition,the stability,phase noise and reference spurs of the charge pump phase-locked loop are analyzed.According to the formulated performances,the loop parameters are designed by using CPPSIM and MATLAB software.2.The phase noise and wideband technology of voltage-controlled oscillator(VCO)are researched and analyzed,and a novel wideband technology of switched coupled transmission line(SCTL)is presented.Fabricated in 45 nm SOI CMOS technology,the VCO with the SCTL achieves 38.74% tuning range(TR)from 39.46 GHz to 58.42 GHz.Compared to the VCO without SCTL,the TR of SCTL-VCO is increased by 29.2% without obvious phase noise deterioration and additional power dissipation.Based on the SCTL-VCO,a low phase noise wideband quadrature VCO(QVCO)is designed with an in-phase injection-coupled network.The post-simulation results show that the QVCO achieves 26.38% TR from 44.23 GHz to 57.67 GHz,the phase noise is-119.0d Bc/Hz~-121.5d Bc/Hz@10MHz,and the quadrature phase error is 2.2o.3.A divider chain including a quadrature injection-locked divider(QILFD),three stage static CML dividers and a NPS programmable divider is designed for the millimeter wave frequency synthesizers.And an ultra-wideband QILFD which uses differential complementary anti-phase injection structure to implement quadrature output and adopts the technologies of SCTL and dual co-tuning with QVCO to improve locking range(LR)is presented.The post-simulation results show that the QILFD achieves 35% LR from 42.6GHz to 60.7GHz,and the quadrature phase error is 0.29o.The division range of three stage CML dividers is 1.5GHz~38.4GHz,and the division ratio of NPS divider is 38~53.4.The nonidealities of frequency phase detector(PFD)and charge pump(CP)is analyzed.Aiming at the optimization of the nonidealities,differential complementary current switches,comparator feedback technology and unity-gain amplifier is adopted to reduce the mismatch of static and dynamic current.And a programmable CP current is designed to keep the loop bandwidth in 700 k Hz~800k Hz.The post-simulation results show that the static current mismatch of CP is less than 0.43%,the reference spurs caused by dynamic current mismatch is-75.4d Bc,and the current noise is-233.1d Bc/Hz@1MHz.5.Based on Fujitsu 55 nm CMOS technology,the whole chip circuit and layout design of frequency synthesizer including above mentioned modules of QVCO,divider chain and PFD/CP and other modules of filter et al are completed.The chip occupies 2.7mm*1.1mm area,and manage to provide the 44.23GHz~57.67 GHz and 22.12 GHz ~28.84 GHz orthogonal output signals.The loop simulation results show that the output phase noise at 56.87 GHz carrier is-90 d Bc/Hz@1MHz and-115 d Bc/Hz@10MHz.And the whole chip post simulation results of the whole chip show that the reference spurs is-68.9d Bc,and the locking time is less than 6?s.