Research And Design On Frequency Synthesizer In Wideband Wireless Transceiver Chip

With the development of wireless communication technologies,many wireless protocols are springing up,leading to fewer wireless spectrum sources and complex airinterface environment.The Software-Defined transveivers are developing toward high integraty,wide bandwidth and multi-modes.The research of this work focus on the frequency synthesizer in the reconfigurable transceiver,aming at low phase noise VCO design,wideband frequency synthesizer design and low quantization noise and fast AFC design.First of all,the wireless network and wireless transceiver are briefly discussed.The spectrum translation process of superheterodyne,zero-IF and low-IF transceivers are discussed for comparison.The calculation process of Gain,NF and linearity of the transceiver are presented.Then,the design specifications of the transceiver and the frequency synthesizer are presented.Secondly,the flicker noise up-conversion and the suppression techniques are presented.Based on the inpulse sensitive function theory,two important parameters that affect the flicker noise up-conversion are analyzed.By introducing a source damping resistor in the cross-coupled pair,the flicker noise could be suppressed.Two VCOs are designed and implemented in TSMC 180 nm CMOS process for verification.The phas noise at 1MHz offset over the tuning range of the two VCOs are-127.2?-132.7 d Bc/Hz and-124.9?-130.9 d Bc/Hz respectively.The measurement results demonstrate that this method is effective and the VCO employing the technique can perform great Fo M in wide tuning range.And then,the frequency extending techniques of frequency synthesizer are presented.The divider seamless switching golden states for correct swapping are presented.In order to mitigate the trade-off between the selectivity and operating range,the passive-negativeresistance based load is proposed.The quadrature single side band mixer utilizing this load is implemented for demonstration.Moreover,the DFF-based divider cannot process the quadrature signals,so the quadrature-in quadrature-out divider is proposed.A 30-3600 MHz frequency synthesizer employing these techniques is implemented in 180 nm CMOS process.The phase noise at 10 k Hz and 1MHz offsets over the entire frequency range are less than-88 d Bc/Hz and-118 d Bc/Hz respectively.The integrated phase noise from 1 k Hz to 10 MHz is less than 2°.The results show that the synthesizer can provide superior performance in a wide tuning range and these techniques can be used in wide FS design.Fourthly,the fast AFC and quantization noise suppression techniques are discussed.The traditional counter-based AFC takes long calibration time,while the proposed one can do that within 1.25?s.By utilizing the forward phase-switching technique,the division step is reduced from 2 to 0.5,suppressing 12 d B quantization noise.A 45-2500 MHz frequency synthesizer utilizing these methods performs phase noise of-99.5 and-123.5d Bc/Hz at 10-k Hz and 1-MHz offsets when the carrier frequency is 2.4GHz and provides the AFC time of1.25?s when 48 MHz reference frequency is used,demonstrating the validity of the phase switching divider and TDC-based AFC.Based on the aforementioned frequency synthesizer and the other blocks,a 45-2500 MHz transceiver is designed and implemented in TSMC 180 nm CMOS process.The measurement results show that the sensitivity of the receiver is-60?-80 d Bm.The transceiver could transfer video within 100 meters without using the external PA.If the external PA is employed,the maximum video transfer distance is around 600 meters.