Design Of PLL Frequency Synthesizer Based On CMOS Techniques

Attribute to the low cost and good performance, Phase-Locked Loop (PLL) which works as a clock synthesizer, has become a necessary and core part in modem microprocessors. It works on the top of the clock tree. Its performance directly influences and decides the highest frequency and stability of the whole chip. The higher the clock frequency is, the more PLL influences the performance of microprocessors. PLL technique has been one of the core techniques in modern microprocessor design.In this paper we described and analyzed the architecture, as well as the block and the mathematical model of charge pump phase locked loop (CPPLL), and then analyzed the linear, nonlinear character and noise character of CPPLL and gave the form for calculating the parameter of CPPLL. Next a CPPLL frequency synthesizer was designed whose working range is 10MHz-80MHz. In order to reduce the influence of noise from supply and substrate, full differential architecture and self-adjusted delay cell is used to keep the output of VCO pure. Stability is good as well. To reduce the dead-zone, a delay unit was added to feedback loop. The designs in this paper are implemented in CSMC 0.8μm CMOS process, the simulation results, layout designs, post-simulation results with Star-Hspice, Hsim and Cadence tools are described, and the test results of chips are reported as well.Simulation results indicate that the frequency synthesizer works well from 2MHz to 100MHz, and provide us a perfect pulse signal within 10μs. Additional chip testing shows that the working temperature range of the frequency synthesizer is -55~125℃, suit for military using.