The Research And Design Of Wide Band CMOS Frequency Synthesizer

The rapidly developing CMOS technology has dramatically lowered the cost of RF component;many components have been realized with Monolithic. The frequency synthesizer formed byPhase-Locked Loop is a critical part of wireless transceivers as it provides RF system with pure,stable and programmable local oscillator signals. Frequency synthesizers with wide band and lowphase noise are the mainstream of industrial products which cater to the needs from diverseapplications.This thesis analyzes the design of the loop parameters and the design method of each block inthe frequency synthesizer based on system and circuit level respectively. A low power and wideband frequency synthesizer implemented in SMIC 65nm CMOS RF technology is taken as anexample.First, the behavior model and methodology in PLL system is introduced. We conclude thedesign flow of frequency synthesizer in system parameters. Then the noise, linear model andspecification are discussed.Second, this thesis briefly introduces the fundamental of oscillators and its classification. Thecircuit structures of narrow-band and wide-band are presented. The typical structures of wide-bandLC VCO are discussed in details. Then the optimization of wide-band VCO with low variation andphase noise are put forward. The factors affecting the phase noise of the LC VCO are obtained inthe end.Third, fundamentals and classification of divider is introduced. Two type of divider applied inFrequency Synthesizer is analyzed, namely programmable divider with prescalers and multi modedivider. Then the advantages and disadvantagse are discussed both in TSPC and SCL structureswhich compose D latch.Finally, according to previous conclusion, a 1.5~3.0GHz integer-N frequency synthesizer withthe reference frequency of 50MHz is implemented in SMIC 65nm CMOS RF technology. It issimulated with Cadence SpectreRF under a 1.2V power supply. The simulation results show that thesettling time of the PLL is less than 10μs.Then VCO is taped out for verification. The whole chipoccupies 0.58×0.67 mm2.The output frequency varies from 1.509~3.095GHz. Each channel isoverlapped by 40% indicating the satisfaction of the coverage over the whole band where the gainvariation is 49.5%. The phase noise of the output is measured to be -115.1dBc/Hz at 1 MHz offsetfrom the carrier of 3.09GHz. The whole circuit consumes 0.85 mA from a 1.2 V supply. The resultsachieved the anticipation of the proposed specifications.