Design Of A Fully Differential 1GHz CMOS PLL Frequency Synthesizer

A Phase Locked Loop (PLL) RF frequency synthesizer with 1GHz output frequency has been designed based on Singapore, Chart0.35μmEE library and 3.3V supply voltage in this paper. Wide loop bandwidth (7MHz) has been used to suppress the phase noise from the Voltage Controlled Oscillator (VCO).The fully differential topology has been adopted to suppress the common mode noise such as the power supply noise, the substrate noise and the environment noise.The whole flow of RF front end design—from the system level to the circuit level has been done. In the system level design, the loop bandwidth has been optimized and the behavior level simulation in time domain has been done using the Simulink tool of Matlab, while in the circuit level design, all the essential blocks have been designed and the whole circuit has been simulated using Cadence Spectre RF.The simulation results show that the output frequency can be locked to 1GHz in ss, typical and ff corners while the settling time is less than 500ns. The phase noise at 500 kHz frequency offset is -103dBc/Hz,-105dBc/Hz,-102dBc/Hz while the spurious tones at 100 MHz are -43.9dBc, -42.6 dBc,-47.2dBc in three corners, separately. When a 25MHz,100mV peak to peak sine wave is added to the supply of all the blocks except the VCO, the output frequency is still 1GHz and the spurious tones at 100MHz is nearly unaffected, while the spurious tones at 25MHz are -48dBc, -48.7 dBc,-51dBc in three corners, separately. The simulation results show that the designed PLL frequency synthesizer meets the design specification and it can be used in the integrated wideband IF with double conversion wireless RF receiver.