Cell Based Synthesized Low Noise All Digital Frequency Synthesizer, 0.13mum CMOS and FPGA Implementations

This thesis proposed an all digital phase locked loop (ADPLL) that consists of a Bang-Bang phase frequency detector (BBPFD) without any cycle-slip and with a narrow dead-zone, a digitally controlled oscillator (DCO) with a built-in low pass filter (LPF), and a multi-modulus divider (MMD) with an extended divide range The loop dynamics and phase noise is simulated by the behavioral simulation in SystemVerilog. The proposed ADPLL is fully synthesized in the field programmable gate array (FPGA) as a fast prototype and is also implemented in 0.13µm complementary metal-oxide semiconductor (CMOS) technology by the standard digital cells and two custom high speed cells. The measured open-loop and closed-loop phase noise of the fabricated CMOS ADPLL are –123.10dBc/Hz and –120.77 dBc/Hz both at 1MHz offset of a carrier of 1.35 GHz.