Research On Low Power Single Gate Nonvolatile Memory

With the development of the’Internet of Things’, the RFID (Radio Frequency Identification), which is the key technology of it, has received wide attention. The RFID system consists of three parts, which are the electronic tag, the reader and the computer server. Since the electronic tag needs to be pasted to the object to be tracked, the demand for it is the largest. This requires that the manufacturing cost of electronic tags is very low. And the tag is usually passive, and the electric energy comes from the sensing current. So the electronic tags need to be low power consumption. However, EEPROM or Flash, which is used to store the information of products in the tag chip, has high manufacturing costs and power consumption, which has caused a huge obstacle to the popularization of RFID.This paper puts forward a low-power single-poly non-volatile memory embeddable in RFID tags. It is designed and implemented in Skysilicon 0.35μm standard CMOS process. The proposed single-poly memory has lower fabricating cost, lower power consumption, more programmable times and simpler control circuits than traditional EEPROM and Flash memory which are implemented in double-poly process. It connects the gates of three MOS as an equivalent floating gate. The capacitive voltage divider principle and Fowler-Nordheim (FN) electron tunneling mechanism is used to charge or discharge the floating gate. The nature that the equivalent floating gate can store either positive charge or negative makes the memory cell could have two data storage patterns. The distinction of them in structure is only that the gate area ratios of the three memory core transistors are different. And the transistors’sizes calculated by the constraint conditions ensure that the storage unit will not be over erased. Erase, write and read operations can be carried out by only two positive voltages to proposed memory cell. The pre-charge operation adopted by the traditional memory is replaced by the operation that presetting the value of the SRAM which is connected to the bit line. Thus, there is no need for the sensitive amplifier. The test results show that the memory has normal storage capabilities and the programming time of the two data storage patterns which were implemented is 80 ms and 120 ms respectively and there is no over-erased and the memory can bear more than 1000 times program cycles.