The Design Of Non-volatile Memory In Standard CMOS Process

RFID tag has the merits of low cost, long operation distance, high read/write speed and operating well under various environments, so it has been widely applied in many application fields, such as logistics, product anti-forgery, target tracking, equipment and asset management. In passive UHF RFID tag chip, an embedded NVM is required to store the information such as security information, electronic product code or user information after power off. The characteristics of the embedded NVM determine many features such as application fields, cost and operation distance of the tag. The design of the NVM is considered to be one of the critical techniques in the tag chip.This paper presents an NVM in0.18μm single-poly CMOS process for passive UHF RFID tag chip, including the key circuits of memory cell, sense amplifier, charge pump, and high voltage switch. To improve its reliability, each memory cell is designed to have double floating gates to store information data. Furthermore, a novel low power operation method is proposed to realize bi-directional FN tunneling during write operation. Moreover, to minimize the area, the cell includes PMOS transistors and coupling capacitors (without NMOS transistors). Gate oxide with thickness of4nm is used as tunneling junction barrier to further reduce the memory size and program/erase voltage.We have designed an ultra-low-power area-efficient NVM with capacity of1Kbits for passive RFID tags. The area of the memory cell and array is96μm2and0.12mm2, respectively. The power consumption of the read/write operation is0.19μW/0.69μW at the read/write rate of (268Kb/s)/(3.0Kb/s). In addition, the endurance characteristics of up to60,000cycles are demonstrated.