The Study Of Non-Volatile Memory Based On Standard CMOS Process

In ASIC circuits, it is often desirable to have available a low-cost, low-density non-volatile memory device. However, process complexity hinders the incorporation of traditional non-volatile memory devices into CMOS circuits. The need for multiple polysilicon layers, different gate oxide thicknesses, and modified junction doping profiles, for example, is responsible for added process complexity and cost. The proposed structure circumvents this problem by creating non-volatile memory cells from standard CMOS transistors. Thus, no additional masking or processing steps are necessary. These advantages in cost and process compatibility make the device useful when small amounts of non-volatile memory are needed for embedded applications.A single poly non-volatile memory cell structure implemented in a standard CMOS process is developed. It is consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysillicon gate. The common gate works as a "floating gate." The inversion layer under the PMOS gate and P+ diffusions works as a "control gate."There are many solutions used to transfer electric charge from and into the FG. For both erase and program, the problem is making the charge pass through a layer of insulating material. In this article we first introduce the two mainly charge Injection mechanisms: The hot-electron injection (HEI) mechanism and The Fowler-Nordheim (FN) tunneling mechanism. The HEI current is often explained and simulated following the "lucky electron" model. The HEI mechanism is usually used for writing the devices and the FN tunneling mechanism is usually used for erasing the devices.The device is simulated by TPROCESS and TDEVICE. We use TPROCESS to simulate the standard CMOS process to build a 3D model of the proposed cell structure and use TDEVICE to simulate the character of the cell. From the simulation results we can observe that this device can be written and erased under proper writing and erasing voltage. I spend the most time on the model building and simulation for it is the vital of the whole project.After simulation of the device, two array architectures are compared and the schematics of these arrays are presented. NOR array architecture is chosen for itscharacter suitable for our design. The layout of 4 X 4 NOR array architecture is proposed and the disturbs of the array are also analyzed.At last the whole schema of the non-volatile memory is presented and two important periphery circuits of the non-volatile memory are proposed and simulated. The Dickson charge pump is used for generate high voltage, and the circuit is improved by limiting the body effect. The sense amplifier is improved from trigger sense amplifier which is usually for DRAM.