Research And Design Of Non-volatile Memory IP Based On Standard CMOS Process

RFID technology(Radio Frequency Identification,RFID)is the use of the radio frequency signal transmission characteristics and spatial coupling,automatic identification of objects to be identified,having read and write distance,speed,non-line reads,strong anti-interference ability and other characteristics in the military and vivil life has been widely used,is the core and foundation technology of things.The electronic tag chip as the core equipment of RFID systems,non-volatile memory(Nonvolatile Memory,NVM)IP core is an important part.Because passive RFID tags operating modes as well as the needs of large-scale applications require the characteristics of the non-volatile memory with ultra-low power consumption(microwatt level),low-cost.Domestic electronic tag chip makers were mostly using UHF RFID chip non-volatile memory based abroad / overseas IP core design process lines abroad / overseas companies to provide these IP cores are expensive,but also in the design and production there is great controllability,controlled by others.The foreign mainstream RFID chip manufacturers have developed their own non-volatile memory IP cores,in terms of cost and power consumption have a great advantage.This paper describes the background of standard CMOS non-volatile memory technology,introduces internationally civilian research progress in terms of standard CMOS non-volatile memory,and discussed the issue of the status of domestic civilian research and faces.Then,analyzes the power to read and write,work parameters on the required temperature,Endurance,etc.,design memory indicators.the standard CMOS process nonvolatile memory system architecture research and design: for UHF RFID chips,presented its structure and function of the composition of the pin definitions.In this paper the design of the memory peripheral circuit,which is designed primarily switching module,the control circuit voltage and the sense amplifier,the charge pump and other circuits are analyzed and part of the design.The simulation results show that the average write-power memory designed for 3.3?W,read power up 2.4?W,meet design specifications.Finally,the design of non-volatile memory in a standard CMOS process flow sheet GSMC 0.13?mCMOS process validation.The test results show that the proposed standard CMOS process design specifications to meet most of the non-volatile memory.