Research And Implementation Of Non-Volatile Memory For UHF RFID Tag Chips In Standard CMOS Process

As a key element in Internet of Things(IOT), the Ultra High Frequency(UHF) Radio Frequency Identification Device(RFID) has been applied worldwide and turn to be the focus of research recently. Non-volatile memory constitutes an important component of UHF RFID chips. With its low cost, low power consumption and other advantages, the non-volatile memory based on standard Complementary Metal-Oxide Semiconductor(CMOS) technologies is becoming more generally preferred in the design of UHF RFID chips.However, because of the relatively large memory cell area, the narrow window of threshold voltage, the high memory read and write power and the low reliability, existing domestic non-volatile memory in standard CMOS processes failed to achieve its application in UHF RFID chips. Therefore, the research and implementation of standard CMOS non-volatile memory technology would greatly sharp domestic UHF RFID chips' performance, playing a significant role in the development of Chinese IOT industry.Firstly, after a brief introduction of the background and thein globally-advanced standard CMOS non-volatile memory, several domestic counterparts are illustrated.Then, a system architecture of non-volatile memory based on standard CMOS is proposed, Aimed at the application in UHF RFID chips, the memory's composition and function pin definition are proposed and its parameter, including power consumption in a typical UHF RFID chip, reading and writing time, operating temperature, etc. are analyzed. A practicable parameter set is demonstrated.After that, a novel memory cell, HPP_CELL, is proposed. The memory cell has a small area(18?m2) and a wide threshold voltage window(about 8V), working out superior performance. A 1K-bit memory array with a test mode is designed to adapt HPP_CELL storage unit's features. As to memory peripheral circuit, voltage switching module is fully designed, while the control circuit,the charge pump, the sense amplifier circuit are analyzed and partly designed. Simulation results indicated that the average power consumption of writing reaches 3.3?W and reading consumes 2.4?W, satisfying the design specifications.Finally, the design in this paper is taped out in GSMC 0.13?m CMOS process, and a dedicated set of tests is performed. Test results indicate that this design meets most of the design specifications and the HPP_CELL memory cell is clearly showing a potential in low power consumption and small area.