Standard CMOS Process-based OTP Memory Design And Research

Low-cost, low-density non-volatile memories are often desired in the design of the ASIC circuit. However, the complexity of the process prevents the traditional non-volatile memory from being embedded in the standard CMOS circuits, resulting from the fact that memories of this kind needs multi-layer polysilicon, different gate oxide thicknesses and the adjustment of different doping concentrations. If the standard CMOS transistors are used to realize non-volatile memories, no additional mask or procedures are necessary, thus, reducing the cost of production.If the standard CMOS transistors are used to create non-volatile memory, thus, no additional mask or process steps are necessary. Based on a standard CMOS process OTP memory cell, a storage density of 32 bits OTP memory is designed. The memory access time is 30ns, the active current is 12.7μA/bit and the standby current is 0.72μA.This paper deals elaborately with the structure of the OTP memory cell which is based on standard CMOS process, and through the analysis of threshold voltage, the mechanism of programming, erasing and accessing of the OTP memory are demonstrated. In circuit design, the working principles and designing methods of the OTP memory function modules are introduced, with the advantages and disadvantages of a variety of architectural analyzed and compared. Besides, good suggestions and solutions are provided for the problems arising in the realization of the memory layout. At the same time, a large number of simulations are done in order to ensure the correctness of memory functions, and the results are verified with the tape out test results.The newly-designed OTP memory has great advantages in cost and process compatibility, bringing it potential market in the embedded applications of small-capacity non-volatile memories.