The Circuit Design Of Physical Layer Of USB2.0 Transceiver

Now human has entered a multimedia era when information is carried in the form of audio and video, and the volume of information is exploding. As we chase for convenience and efficiency of information transportation, a highly efficient data transporting interface becomes a hotspot for both market and research. In this dissertation, the work will focus on the research and design of the most promising interface for information storage and exchange, the USB2.0 transceiver, and the high speed mode capable transceiver are implemented.In order to provide higher efficiency, the USB interface has developed from low speed mode to high speed mode. However the high speed mode imposes more critical restriction on the circuit design. In low speed case, the transceiver is designed to supply enough drive strength. But for high speed mode, much more consideration should be payed. Firstly, the impact of process parameters’uncertainty and temperature variation on the driver impedance must be taken into account, for the impedance mismatch leads to the problem of signal attenuation. Secondly, the high susceptibility of noise coupling from working environment would result in the problem of misjudgement of signal level. Lastly, how the high speed serial data bits could be recovered effectively. We will directly face to all these problems and make innovative design to resolve them.Based on the idea of dynamic matching, we design a transceiver with impedance calibration ability that supports both high speed and full speed mode. And the simulation shows that the innovative structure effectively overcomes the problem of process parameters’uncertainty and temperature variation by providing pretty well impedance match, which insures the signal integrity and complies with the specification.Impedance match is just one necessary precondition to assure reliable high speed communication. We still need some scheme to get rid of the high noise sensitivity of high speed signal. A voltage envelop detector is designed to validate the physical signal level according to the USB2.0 specification. And due to the fact of level comparison, the same circuit structure is adopted to implement the link disconnection detector in high speed mode, which exploits the reusability of circuit module.At last, after a through exploration of the phase locked loop system, some design principles are summarized in the work, and the traditional single-end controlled VCO is innovatively modified to a dual-end controlled one, and a stable 480MHz charge pump phase-locked loop with 8-phase output is designed. With these multi-phase clocks, the over-sampling data recovery technology based on data edge information and sliding window is improved, which effectively increase the correctness of data recovery in high speed mode.From a general point of view, USB is a communication interface protocol proposed for high speed, effective and reliable data transportation. The specification covers both the data link layer and the physical layer. This work emphasizes on research and design of the transceiver in physical layer with signal integrity and circuit stability in special consideration according to the specification. And the design principles and techniques can be applied to similar high speed serial data communication circuit design.