Used In Uwb Systems, Low-power Frequency Synthesizer Design And Research

The CMOS frequency synthesizers and the phase-locked loops(PLLs) have been widely utilized in many modern wireless communication systems.Low phase noise, small area and low power consumption are the essential requirements for mobile electronic systems.To reduce power and area,the output phase noise maybe be increased, and vice versa.So the design of PLLs must generally deal with a trade-off between the power/area and the output phase noise.This thesis takes the design of low power and small area frequency synthesizer with top-down design as objective.The design of loop parameters and noise evaluation of frequency synthesizer are analyzed through the design on system and circuit level.A low voltage and high speed frequency synthesizer is implemented in SMIC 0.13um CMOS process.From the aspect of system design,design flow of system parameters are obtained through the analysis of three orders s-domain of closed-loop.Based on the design flow, loop parameters which meet the system stability can be figured out.In order to reduce area and power,the charge current of Charge-Pump should be selected as small as possible to reduce resister and capacitors of loop filter.Since the ring oscillator,which has worse noise performance than LC tank,is used in this thesis,bigger loop bandwidth is selected to minimize noise impact caused by ring oscillator for high pass characteristic of VCO to the output of frequency synthesizer.From the aspect of VCO design,the detailed analysis includes the working principle, the circuit structures and noise models.And the noise models can guide the noise optimization of circuit design.From the aspect of circuits design,a charge pump worked under the low voltage supply is designed.Its current of match is simulated and verified.Fully differential symmetrical delay cell is employed in voltage controlled oscillator.Compared to single ended ring oscillator,circuit topology chosen in this thesis is more capable of suppressing noise from substrate and power supply.It can also obtain both multiphase outputs and higher operation frequency.In order to reduce substrate noise disturbing,the capacitor of loop filter is realized by using PMOS.Finally,the frequency synthesizer is implemented in SMIC 0.13um CMOS process with 1.2V power supply voltage.The output frequency is 528MHz and 132MHz.The core area is 0.02mm,and the total power is 2.4mW when the output frequency is 528MHz.The output phase noise is -104dB/Hz@1MHz and the RMS jitter is 15ps.