Difference Time-domain Comparator, Successive Approximation Adc Research And Design

Recently, the international research applying on biomedical systems and wireless micro-sensor network attracts more and more attention. Sound, pressure, temperature and so on are acquired and converted to electrical signals by the sensors in the front-end of these SOC systems, and then converted to digital codes by analog-to-digital (A/D) converters for the data signal processing (DSP) in the back-end. These systems are usually powered by battery, so power-efficient IC is necessary. The successive approximation register (SAR) A/D converter can meet the requirements of precision and speed in these applications with very low power. So it has become the most suitable type of A/D converters for the data acquisition systems.A 12-bit,200KS/s SAR A/D converter based on the time domain comparator is studied and designed in this thesis. A new differential time domain comparator is proposed based on the time domain comparator. The input voltages of the time domain comparator are converted to pulses and detected by the phase detector to generate comparison result. In this thesis, fully differential is used for the comparator to suppress the common mode noise, and the input offset of comparator is cancelled by charge pumps instead of preamplifiers, which reduces the power consumption and realizes the on-chip offset cancellation. The digital-to-analog (D/A) converters is implemented in capacitor array with an attenuation capacitor with less area and power than the conventional binary weighted capacitor array. The value of unit capacitor is determined according to the simulation on nonlinearity of the D/A converter caused by capacitor mismatch. The proportional ratio edge layout is adopted for capacitor arrays to minimize the nonlinearity caused by processing and parasitic capacitance.The chip is manufactured in SMIC 0.18μm CMOS process, and the total area is 2mm×2mm. The test results show the DNL is 1.3/-1.0LSB and the INL is 3.6/-3.45LSB. The SNDR is 59.3dB which equals to an ENOB of 9.56 bit at a sampling frequency of 200 KHz and an input frequency of 87 KHz. The total power consumption is 72p.W with 1.8V supply, and the Figure-of-Merit is 477fJ/conv.-step.